SDRAM controller for parallel processor architecture

• US 6,983,350 B1
• Filed: 08/31/1999
• Issued: 01/03/2006
• Est. Priority Date: 08/31/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wheeler, William R., Wolrich, Gilbert, Adiletta, Matthew J., Burres, Bradley
• Primary Examiner(s): Sparks, Donald
• Assistant Examiner(s): DILLER, JESSE DAVID
• Application Number:
  US09/387,109
• Time in Patent Office: 2,317 Days
• Field of Search: 711/151, 711/158, 710/39, 710/57, 710/52, 710/40, 710/241
• US Class Current: 711/151
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Claims

1. A controller for a random access memory comprises:

an address and command queue that holds memory references from a plurality of microcontrol functional units;

a first read/write queue that holds memory references from a computer bus;

a second read/write queue that holds memory references from a core processor; and

control logic including an arbiter that detects the fullness of each of the queues and a status of outstanding memory reference to select a memory reference from one of the queues, wherein the control logic is responsive to an optimized memory bit and a chaining bit, and wherein assertion of the chaining bit will control the arbiter when the optimized memory bit is also set to maintain the memory references from a current queue.

2. The controller of claim 1 wherein the control logic further selects one of the queues to provide a next memory reference based on a programmable value stored in a priority service control register.

3. The controller of claim 1 wherein the address and command queue comprises:

a high priority queue that holds memory references from high priority tasks.

4. The controller of claim 1 wherein the address and command queue comprises:

an even bank queue;

an odd bank queue; and

wherein a microengine sorts memory references into odd bank and even bank references.

5. The controller of claim 4 wherein the address and command queue comprises:

an order queue and wherein controller examines an optimized memory reference bit and if set, causes incoming reference requests to be sorted into either the even bank queue or the odd bank queue.

6. The controller of claim 5 wherein the address and command queue comprises:

an order queue; and

wherein if the memory reference request does not have a memory optimization bit set, the memory reference is stored in the order queue.

7. The controller of claim 1 wherein the address and command queue is implemented in a single memory structure and comprises:

an order queue for storing memory references;

an even bank queue for storing memory references;

an odd bank queue for storing memory references;

a high priority queue for storing memory references; and

with the memory structure being segmented into four different queue regions, each region having its own head and tail pointer.

8. The controller of claim 7 wherein the address and command queue further comprises:

an insert queue control and a remove queue arbitration logic to control insert and removal of memory references from the queues.

9. The controller of claim 1 further comprising:

a command controller and address generator that is responsive to an address from a selected memory reference from one of said queues, to produce addresses and commands to control a memory interface.

10. The controller of claim 9 further comprising:

a memory interface responsive to generated addresses and commands to produce memory control signals.

11. The controller of claim 1 wherein the control logic is responsive to a chain bit that when set allows for special handling of contiguous memory references.

12. The controller of claim 11 wherein assertion of the chain bit will control the arbiter to have the arbiter select the functional unit which previously requested that bus because setting of the chain bit indicates that the microcontrol functional unit issued a chain request.

13. The controller of claim 1 wherein the arbiter has an arbitration policy that favors chained memory references.

14. The controller of claim 13 wherein the arbiter has an arbitration policy that services chained requests until a chain bit is cleared.

15. The controller of claim 1 wherein the arbiter has an arbitration policy that starts by examining for chained memory reference requests.

16. The controller of claim 15 wherein the arbitration policy enables chained memory requests to be serviced completely.

17. The controller of claim 15 wherein when a chain bit is set, the arbitration engine services the same queue again until the chain bit is cleared.

18. A controller for a random access memory comprises:

an address and command queue that holds memory references from a plurality of microcontrol functional units;

a first read/write queue that holds memory references from a computer bus;

a second read/write queue that holds memory references from a core processor; and

control logic including an arbiter that detects the fullness of each of the queues and a status of outstanding memory reference to select a memory reference from one of the queues, wherein the address and command queue comprises;

an even bank queue;

an odd bank queue;

an order queue;

wherein a microengine sorts memory references into odd bank and even bank references; and

wherein controller examines an optimized memory reference bit and if set, causes incoming reference requests to be sorted into either the even bank queue or the odd bank queue.

19. The controller of claim 18 wherein the address and command queue comprises:

an order queue; and

wherein if the memory reference request does not have a memory optimization bit set, the memory reference is stored in the order queue.

20. A controller for a random access memory comprises:

an address and command queue that holds memory references from a plurality of microcontrol functional units;

a first read/write queue that holds memory references from a computer bus;

a second read/write queue that holds memory references from a core processor; and

control logic including an arbiter that detects the fullness of each of the queues and a status of outstanding memory reference to select a memory reference from one of the queues, wherein the address and command queue is implemented in a single memory structure and comprises;

an order queue for storing memory references;

an even bank queue for storing memory references;

an odd bank queue for storing memory references;

a high priority queue for storing memory references; and

with the memory structure being segmented into four different queue regions, each region having its own head and tail pointer.

21. The controller of claim 20 wherein the address and command queue further comprises:

an insert queue control and a remove queue arbitration logic to control insert and removal of memory references from the queues.