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Microprocessor chip simultaneous switching current reduction method and apparatus

  • US 6,983,387 B2
  • Filed: 10/17/2002
  • Issued: 01/03/2006
  • Est. Priority Date: 10/17/2002
  • Status: Active Grant
First Claim
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1. A method for reducing simultaneous switching current in a microprocessor chip, comprising:

  • partitioning the chip into multiple independent processor cores, each with an associated clock domain;

    generating a clock signal;

    independently delaying the clock signal to produce multiple independent phase-staggered clock signals, each said signal being distributed to a differing said core and clock domain;

    defining a plurality of intra-chip functions including high-speed I/O (input/output) latches and drivers associated with each of said cores; and

    distributing said intra-chip functions over the area of said chip in each of said cores clustered into areas corresponding and proximal to each said clock domain.

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