Microprocessor chip simultaneous switching current reduction method and apparatus

• US 6,983,387 B2
• Filed: 10/17/2002
• Issued: 01/03/2006
• Est. Priority Date: 10/17/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hofstee, Harm Peter, Boerstler, David William, Dhong, Sang Hoo, Liu, Peichun Peter
• Primary Examiner(s): Cottingham, John R.
• Application Number:
  US10/273,617
• Publication Number:
  US 20040078613A1
• Time in Patent Office: 1,174 Days
• Field of Search: 713/322
• US Class Current: 713/322
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

Disclosed is an electronic chip containing a plurality of electronic circuit partitions, distributed over the area of the chip, each including a processor core and a clock phase domain different from cores in other partitions of the chip. A source of same frequency, but different phase clock signals representing different clock domains, provides different phase signals to adjacent partitions for the purpose of reducing instantaneous magnitude switching currents. Intra-chip communication circuitry distributes control and data signals between partitions.

Claims

1. A method for reducing simultaneous switching current in a microprocessor chip, comprising:

partitioning the chip into multiple independent processor cores, each with an associated clock domain;

generating a clock signal;

independently delaying the clock signal to produce multiple independent phase-staggered clock signals, each said signal being distributed to a differing said core and clock domain;

defining a plurality of intra-chip functions including high-speed I/O (input/output) latches and drivers associated with each of said cores; and

distributing said intra-chip functions over the area of said chip in each of said cores clustered into areas corresponding and proximal to each said clock domain.

8. The method of claim 1, wherein the step of independently delaying the clock signal further comprises providing the clock signal to a plurality of independent delay circuits.

2. An electronic package including a plurality of separately partitioned microprocessor functions, comprising:

a clock signal generator;

independent delay circuitry to produce multiple independent phase-staggered clock signals, each clock signal providing same frequency but different phase output;

a plurality of electronic circuit partitions, distributed over the area of said electronic package, each including an independent processor core and an independent clock phase domain different from cores in other partitions of said electronic package;

intra-chip communication circuitry, associated with each of said cores, including I/O (input/output) latches and drivers; and

circuit paths between the clock signal generator and the circuit partitions whereby different phase clock signals are provided to different partitions.

9. The electronic package of claim 2, wherein independent delay circuitry further comprises a plurality of independent delay circuits.

10. The electronic package of claim 9, wherein each delay circuit of the plurality of delay circuits is directly connected to the clock signal generator.

11. The electronic package of claim 2, wherein the clock signal generator is a phase-locked loop (PLL).

3. A method of communicating between a plurality of microprocessors on a single electronic chip, comprising:

partitioning the chip into a plurality of areas;

placing some of the processors and associated intra-chip input/output circuitry in different partitions where different independent partitions have different clock domains;

generating a clock signal; and

independently delaying the clock signal to provide same frequency but different phase independent clock signals to each of said partitions having different clock domains whereby load switching currents occur at different times for each of said clock domains.

12. The method of claim 3, wherein the step of independently delaying the clock signal further comprises providing the clock signal to a plurality of independent delay circuits.

4. A method for reducing simultaneous switching current in a microprocessor chip, comprising:

partitioning the chip into multiple independent processor cores, each with an associated clock domain, each of the partitions including associated intra-chip input/output functionality;

generating a clock signal; and

independently delaying the clock signal to provide same frequency but different phase independent clock signals to the processor cores in each of said partitions whereby load switching currents occur at different times for each of said clock domains.

13. The method of claim 4, wherein the step of independently delaying the clock signal further comprises providing the clock signal to a plurality of independent delay circuits.

5. An electronic package including a plurality of separately partitioned microprocessor functions, comprising:

a plurality of electronic circuit partitions, distributed over the area of said electronic package, each including an independent processor core and an independent clock phase domain different from cores in other partitions of said electronic package;

intra-chip communication circuitry, associated with said cores in each of said partitions; and

delay circuitry to produce multiple independent clock signals of same frequency but different phase output providing different phase clock signals to different partitions.

14. The electronic package of claim 5, wherein the delay circuitry further comprises a plurality of independent delay circuits.

15. The electronic package of claim 14, wherein each delay circuit of the plurality of delay circuits is directly connected to a clock signal generator.

16. The electronic package of claim 15, wherein the clock signal generator is a PLL.

6. A method for reducing simultaneous switching current in a microprocessor chip, comprising the steps of:

interconnecting a plurality of independent microprocessors using different intra-chip input/output circuitry, comprising latches and drivers, for each microprocessor;

generating a clock signal; and

independently delaying the clock signal to provide same frequency but different phase independent output clock signals to different ones of said different intra-chip input/output circuitry.

17. The method of claim 6, wherein the step of independently delaying the clock signal further comprises providing the clock signal to a plurality of independent delay circuits.

7. An electronic package including a plurality of separately partitioned microprocessor functions, comprising:

a clock signal generator;

a plurality of independent delay circuits, wherein each delay circuit is directly connected to the clock signal generator and produces a different independent phase-staggered clock signal, wherein the plurality of phase-staggered clock signals provide the same frequency but different phase output;

a plurality of electronic circuit partitions, distributed over the area of said electronic package, each including an independent processor core and an independent clock phase domain different from cores in other partitions of said electronic package, wherein each electronic circuit partition is connected to the output of a different delay circuit of the plurality of delay circuits; and

intra-chip communication circuitry, associated with each of said cores, including I/O (input/output) latches and drivers.

18. The electronic package of claim 7 wherein the clock signal generator is a PLL.