Vertically integrated photosensor for CMOS imagers

• US 6,984,816 B2
• Filed: 08/13/2003
• Issued: 01/10/2006
• Est. Priority Date: 08/13/2003
• Status: Active Grant

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Candelaria, Jon J., Holm, Paige M.
• Primary Examiner(s): Le, Que T.
• Application Number:
  US10/641,216
• Publication Number:
  US 20050040316A1
• Time in Patent Office: 881 Days
• Field of Search: None
• US Class Current: 250/214.00R
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

An exemplary system and method for providing a vertically integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS layer (420); and a photosensing element (380) fabricated in a vertically integrated optically active layer (320, 350), where the optically active layer (320, 350) is bonded to the CMOS layer (420) and the optically active layer (320, 350) is positioned near a metalization surface (405) of the CMOS layer (420). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated photosensing components that may be readily incorporated with existing technologies for the improvement of CMOS imaging, device package form factors, weights and/or other manufacturing, device or material performance metrics.

Claims

1. A method for making an electronic imaging component, said method

comprising the steps of:

providing an electronics layer;

providing a photosensing element, said photosensing element fabricated in a vertically integrated optically active layer;

providing a substantially vertical interconnect;

providing a junction substantially surrounding and at least partially encompassing said vertical interconnect, wherein charge carriers may be substantially laterally drawn toward the axis of at least one of said junction and said interconnect;

bonding said optically active layer to said electronics layer, wherein said optically active layer is disposed substantially proximate to a metalization surface of said electronics layer.

2. The method of claim 1, wherein said electronics layer is substantially fully processed.

3. The method of claim 1, wherein said photosensing element comprises at least one of a photodiode, a photomultiplier, a phototransistor, and a photoconductor.

4. The method of claim 1, wherein said optically active layer comprises at least one of Si, GaAs, InP, GaN, HgCdTe, a-Si, p-Si, p-Si, x-Si, Ge, SiGe, SiC, a monocrystalline material, a polycrystalline material and an amorphous material.

5. The method of claim 1, wherein said bonding comprises at least one of wafer-to-wafer bonding and die-to-wafer bonding.

6. The method of claim 1, wherein said interconnect comprises at least one of a metallized via, an electrical conductor, p-Si and a semiconductor;

and said interconnect extends substantially through said optically active layer.

7. A method for making an electronic imaging component array, said method comprising the steps of:

providing an electronics array layer;

providing a photosensing element array, said photosensing element array fabricated in a vertically integrated optically active layer;

providing a plurality of substantially vertical interconnects;

providing a plurality of junctions substantially surrounding and at least partially encompassing said plurality of vertical interconnects, wherein charge carriers may be substantially laterally drawn toward the axes of at feast one of said plurality of junctions and said plurality of interconnects;

bonding said optically active layer to said electronics layer, wherein said optically active layer is disposed substantially proximate to a metalization surface of said electronics layer.

8. The method of claim 7, wherein said plurality of vertical interconnects comprises a density of about one connection per up to about 10–

250 square microns.

9. The method of claim 7, wherein said plurality of interconnects comprise a plurality of at least one of metallized vias, electrical conductors, p-Si and semiconductors.

10. The method of claim 7, wherein the photosensing element fill factor is up to about 75%.

11. The method of claim 7, wherein the photosensing element fill factor is greater than 75%.

12. The method of claim 11, wherein the photosensing element fill factor is up to about 100%.

13. The method of claim 7, wherein the electronic processing circuitry is optimized for substantial parallel processing of array-captured images.

14. The method of claim 7, further comprising the step of providing a plurality of vertically integrated optically active layers.

15. The method of claim 7, further comprising the step of providing a plurality of vertically integrated electronics layers.

16. The method of claim 7, wherein said optically active layer comprises at least one of Si, GaAs, InP, GaN, HgCdTe, a-Si, p-Si, x-Si, Ge, SiGe, SiC, a monocrystalline material, a polycrystalline material, and an amorphous material.