Customizable and programmable cell array

• US 6,985,012 B2
• Filed: 08/27/2004
• Issued: 01/10/2006
• Est. Priority Date: 03/10/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi
• Primary Examiner(s): Mai, Lam T.
• Application Number:
  US10/927,470
• Publication Number:
  US 20050024086A1
• Time in Patent Office: 501 Days
• Field of Search: 326/41, 326/38, 326/101, 326/102, 326/103, 326/39, 326/47
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H03K 19/1732 by limitation or reduction of the pin/gate ratio for data-processing equipment G06F1/22
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A logic array may include an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Claims

1. A logic array comprising:

an array of logic cells having a multiplicity of inputs and a multiplicity of outputs;

wherein each of at least some of said logic cells comprises at least one look-up table; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs;

wherein said customized interconnections comprise at least two customized metal layers overlying said logic cells,

wherein each of said logic cells also comprises at least one multiplexer, and wherein at least some of said multiplexers are configured to perform a logic operation by said customized interconnections.

2. A logic array comprising:

an array of logic cells having a multiplicity of inputs and a multiplicity of outputs;

wherein each of at least some of said logic cells comprises at least one look-up table; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs;

wherein said customized interconnections comprise at least two customized metal layers overlying said logic ceils,

wherein said look-up table is customized by a custom layer.

3. A logic array comprising:

an array of logic cells having a multiplicity of inputs and a multiplicity of outputs;

wherein each of at least some of said logic cells comprises at least one look-up table; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs;

wherein said customized interconnections comprise at least two customized metal layers overlying said logic cells,

wherein said customized interconnections comprise at least three customized metal layers overlaying said logic cells.

4. A logic array comprising:

an array of logic cells having a multiplicity of inputs and a multiplicity of outputs;

wherein each of at least some of said logic cells comprises at least one look-up table; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs;

wherein said customized interconnections comprise at least two customized metal layers overlying said logic cells,

wherein said customized metal layers are formed using direct write e-beam technology.

5. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table and at least one inverter, said inverter having an inverter input and an inverter output, wherein said inverter input and inverter output are part of said multiplicity of inputs and multiplicity of outputs;

said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various ones of said inputs and outputs in a customized manner.

6. A semiconductor device according to claim 5, wherein at least one of said logic cells also comprises at least one multiplexer, and wherein said multiplexer is configured to perform a logic function by said metal connection layers.

7. A semiconductor device according to claim 6, wherein said logic function is selected from the group of logic functions consisting of:

NAND, NOR, AND, OR, and XOR.

8. A semiconductor device according to claim 5, wherein said metal connection layers comprise at least two customized metal layers.

9. A semiconductor device according to claim 5, wherein said metal connection layers comprise at least three customized metal layers.

10. A semiconductor device according to claim 5, wherein said standard metal layer comprises at least one metal strip, and wherein said metal strip has at least two vias overlying it.

11. A semiconductor device according to claim 5, wherein said look-up table is customized by a custom layer.

12. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table and at least one simple logic gate, said logic gate having at least one logic gate input and logic gate output, wherein at least some of said logic gate inputs are part of said multiplicity of inputs;

said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various ones of said inputs and outputs in a customized manner.

13. A semiconductor device according to claim 12, wherein at least one said logic cell also comprises an inverter, said inverter having an inverter input and an inverter output, wherein said inverter input and inverter output are part of said at least one input and at least one output.

14. A semiconductor device according to claim 12, wherein said logic gate is a buffer.

15. A semiconductor device according to claim 12, wherein said look-up table is customized by a custom layer.

16. A semiconductor device according to claim 12, wherein said standard metal layer comprises at least one metal strip, and wherein said metal strip has at least two vias overlying it.

17. A semiconductor device according to claim 12, wherein said logic cells also comprise at least one multiplexer, and wherein said multiplexer is configured to perform a logic function by said metal connection layers.

18. A semiconductor device according to claim 12, wherein said metal connection layers comprise at least two customized metal layers.

19. A semiconductor device according to claim 12, wherein said metal connection layers comprise at least three customized metal layers.

20. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table and at least one multiplexer, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one of said multiplexers is configured to perform a two-input logic function by said metal connection layers,

wherein said look-up table is customized by a custom via layer.

21. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table and at least one multiplexer, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one of said multiplexers is configured to perform a two-input logic function by said metal connection layers,

wherein said standard metal layer comprises at least one metal strip, and wherein said metal strip has at least two vias overlying it.

22. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table and at least one multiplexer, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one of said multiplexers is configured to perform a two-input logic function by said metal connection layers,

wherein said metal connection layers comprise at least three customized metal layers.

23. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one interconnection within said logic cell is made by said metal connection layers,

wherein said standard metal layer comprises at least one metal strip, said metal strip having at least two vias overlying it.

24. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one interconnection within said logic cell is made by said metal connection layers,

wherein said metal connection layers comprise at least one custom via layer and at least two custom metal layers.

25. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one interconnection within said logic cell is made by said metal connection layers,

wherein said logic array also comprises a multiplicity of multiplexers, wherein at least one of said multiplexers is configured to perform a logic function by said metal connection layers.

26. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one interconnection within said logic cell is made by said metal connection layers,

wherein said logic function is selected from the group of logic functions consisting of;

NAND, NOR, AND, OR, and XOR.

27. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one interconnection within said logic cell is made by said metal connection layers,

wherein said logic cells includes at least one simple logic gate selectably connected to at least one of said multiplicity of inputs or at least one of said multiplicity of outputs.

28. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one interconnection within said logic cell is made by said metal connection layers,

wherein said logic array comprises at least one simple logic gate, said logic gate having a logic gate input, and wherein said metal connection layers also interconnect said logic gate input with one or more of said outputs in a customized manner.

29. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs;

each logic cell including at least two look-up tables and at least one flip-flop;

said logic array also comprising metal connection layers overlying said logic array for interconnecting various ones of said inputs and outputs in a customized manner.

30. A semiconductor device according to claim 29, wherein said metal connection layers comprise at least three customized metal layers.

31. A semiconductor device according to claim 30, wherein said logic array comprises at least two standard metal layers.

32. A semiconductor device according to claim 29, wherein said look-up table is customized by a custom via layer.

44. A semiconductor device according to claim 29, wherein at least one said logic cell includes at least one inverter.

33. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table, said logic array also comprising at least one simple logic gate and one standard metal layer;

said logic gate having at least one logic gate input and logic gate output,

and metal connection layers overlying said logic array for interconnecting various ones of said inputs and outputs and said logic gate input;

in a customized manner.

34. A semiconductor device according to claim 33, wherein at least one said logic cell also comprises an inverter, said inverter having an inverter input and an inverter output, wherein said inverter input or inverter output is part of said multiplicity of inputs and multiplicity of outputs.

35. A semiconductor device according to claim 33, wherein said logic gate is a buffer.

36. A semiconductor device according to claim 33, wherein said look-up table is customized by a custom layer.

37. A semiconductor device according to claim 33, wherein said standard metal layer comprises at least one metal strip, and wherein said metal strip has at least two vias overlying it.

38. A semiconductor device according to claim 33, wherein at least one of said logic cells also comprises at least one multiplexer, and wherein said multiplexer is configured to perform a logic function by said metal connection layers.

39. A semiconductor device according to claim 33, wherein said metal connection layers comprise at least two customized metal layers.

40. A semiconductor device according to claim 33, wherein said metal connection layers comprise at least three customized metal layers.

41. A semiconductor device according to claim 33, wherein said logic gate is an inverter.

42. A semiconductor device according to claim 33, wherein said logic gate is a NAND.

43. A semiconductor device according to claim 33, wherein said logic gate is a NOR.

45. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one interconnection within said logic cell is made by said metal connection layers,

wherein a multiplicity of said interconnections within said logic cell is made by said metal connection layers.

46. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one interconnection within said logic cell is made by said metal connection layers,

wherein at least one of said logic cells includes at least two look-up tables, and wherein at least one of said interconnections within said logic cell is between an output of a first of said look-up tables and an input of a second of said look-up tables.

47. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one look-up table, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one interconnection within said logic cell is made by said metal connection layers,

wherein at least one of said logic cells includes at least one look-up table and at least one inverter; and

wherein at least one of said interconnections within said logic cell is between an output of one of said look-up tables and an input of one of said inverters.