Memory circuit and coherent detection circuit

• US 6,985,468 B2
• Filed: 02/01/2001
• Issued: 01/10/2006
• Est. Priority Date: 02/03/2000
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Arimura, Takuya
• Primary Examiner(s): NGUYEN, HANH N
• Application Number:
  US09/926,241
• Publication Number:
  US 20020159469A1
• Time in Patent Office: 1,804 Days
• Field of Search: 370/235, 370/335, 370/311, 370/320, 370/321, 370/329, 370/350, 370/412, 370/419, 370/420, 375/324, 375/316, 375/325, 375/147, 375/240.24
• US Class Current: 370/335
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 2201/70701 featuring pilot assisted reception
• CPC Class Codes: H04B 2201/70711 with modular structure
• CPC Class Codes: H04J 13/0077 Multicode, e.g. multiple codes assigned to one user

Abstract

The memory circuit of the present invention temporarily stores information symbols included in a reception signal according to a CDMA system which allows multi-code communication to carry out coherent detection using a pilot symbol. The memory circuit of the present invention is constructed of a plurality of electrically independent memory blocks. Each memory block corresponds to one code and one slot of an information symbol. Write access and read access to memory blocks are generated periodically on condition that write access and read access to one memory block do not occur simultaneously. Blocks to which no access is generated are forcibly set to a low power consumption mode to reduce power consumption caused by accesses.

Claims

1. A memory circuit for temporarily storing information symbols to receive a signal according to a CDMA system which allows multi-code communication and to perform coherent detection using a pilot symbol, the memory circuit comprising:

a plurality of electrically independent memory blocks, each memory block being associated with a code in the multi-code communication and a slot in a reception signal; and

a memory interface that periodically performs data write and data read with said plurality of blocks so as not to allow write access and read access to one memory block at a same time;

wherein the memory interface selectively accesses a memory block associated with a slot subject to coherent detection and a memory block associated with a slot currently being received.

2. The memory circuit of claim 1, further comprising:

a memory operation controller that sets memory blocks to which no access is made in a low power consumption mode.

3. The memory circuit according to claim 2, wherein the low power consumption mode of the memory blocks is implemented by stopping supply of an operating clock.

4. The memory circuit of claim 1, wherein said memory interface periodically performs data write and data read with said plurality of blocks so as not to allow write access to one memory block during a read access to said one memory block, and so as not to allow a read access to said one memory block during a write access to said one memory block.

5. An information symbol storage memory access control method, comprising:

providing an information symbol storage memory in which a memory area is divided into a plurality of electrically independent memory blocks based on at least one of information about the number of multi-codes and slot information;

selectively accessing a memory block associated with a slot subject to coherent detection and a memory block associated with a slot currently being received; and

periodically performing data write and data read with the plurality of blocks so as not to allow write access and read access to one memory block at a same time.

6. The information symbol storage memory access control method of claim 5, wherein said periodically performing comprises periodically performing data write and data read with said plurality of blocks so as not to allow write access to one memory block during a read access to said one memory block, and so as not to allow a read access to said one memory block during a write access to said one memory block.