Packetized data transmissions in a switched router architecture

• US 6,985,484 B1
• Filed: 06/28/2001
• Issued: 01/10/2006
• Est. Priority Date: 01/09/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Tornes, James E., Miller, Steven C.
• Primary Examiner(s): LEE, CHI HO A
• Application Number:
  US09/896,370
• Time in Patent Office: 1,657 Days
• Field of Search: 370/389, 370/392, 370/400, 370/401, 370/465, 370/468, 370/386, 370/381, 370/382
• US Class Current: 370/392
• CPC Class Codes: H04L 49/253 using establishment or release of connections between ports
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports

Abstract

A switched router for transmitting packetized data concurrently between a plurality of devices coupled to the switched router. The devices are coupled to the I/O ports of the switched router. The switched router is then programmed to route packets of data from various source ports to several destination ports. Different packets may be transmitted concurrently through the switched router. The packets are comprised of a command word containing information corresponding to packet routing, data format, size, and transaction identification. Furthermore, the command word may include a destination identification number for routing the packet to a destination device, a source identification number used by a destination device to send back responses, a transaction number to tag requests that require a response, and a packet type value indicating a particular type of packet. In addition, there may be bits within a packet used to indicate a coherent transaction, guarantee bandwidth, an error during transmission, or a sync barrier for write ordering. Other types of packets may include a fetch and operation packet with increment by one, a fetch and operation packet with decrement by one, a fetch and operation packet with clear, a store and operation packet with increment by one, a store and operation packet with decrement by one, a store and operation packet with a logical OR, and a store and operation packet with a logical AND.

Claims

1. An apparatus for transmitting packets of data concurrently between a plurality of devices, comprising:

a switching matrix having a plurality of ports programmed to route packets from a source port to one of several destination ports, wherein the packets are comprised of a command word containing information corresponding to packet routing, data format, size, and transaction identification;

a first device coupled to the switching matrix;

a second device coupled to the switching matrix;

a third device coupled to the switching matrix, wherein the third device can transmit a first packet to the first device or the second device while the second device transmits a second packet to either the first device or the third device and while the first device transmits a third packet to either the second device or the third device, wherein each packet includes a coherent transaction bit that determines whether a packet is to be included in a coherent memory operation.

2. The apparatus of claim 1, wherein the command word includes a destination identification number for routing the packet to a destination device.

3. The apparatus of claim 1, wherein the command word includes a source identification number used by a destination device to send back responses.

4. The apparatus of claim 1, wherein the command word includes a transaction number to tag requests that require a response.

5. The apparatus of claim 1, wherein the command word includes a packet type value indicating a particular type of packet.

6. The apparatus of claim 1, wherein each packet is one of a request packet and a response packet, the request packet operable to initiate an operation to take place, the response packet operable to provide a reply for a request packet.

7. The apparatus of claim 1, wherein the command word includes a bit to guarantee bandwidth.

8. The apparatus of claim 1, wherein the command word includes an error bit which indicates whether an error occurred during transmission.

9. The apparatus of claim 1, wherein the command word includes a bit that is used as a sync barrier for write ordering.

10. The apparatus of claim 1, wherein a packet corresponds to a fetch and operation packet with increment by one.

11. The-apparatus of claim 1, wherein a packet corresponds to a fetch and operation packet with decrement by one.

12. The apparatus of claim 1, wherein a packet corresponds to a fetch and operation packet with clear.

13. The apparatus of claim 1, wherein a packet corresponds to a store and operation packet with increment by one.

14. The apparatus of claim 1, wherein a packet corresponds to a store and operation packet with decrement by one.

15. The apparatus of claim 1, wherein a packet corresponds to a store and operation packet with a logical OR.

16. The apparatus of claim 1, wherein a packet corresponds to a store and operation packet with a logical AND.

17. The apparatus of claim 1, wherein a packet corresponds to a special packet.

18. The apparatus of claim 1, wherein a packet includes sideband bits which are used to transfer information between sending and receiving devices.

19. A method for transmitting packets of data concurrently between a plurality of devices, comprising the steps of:

programming a switching matrix having a plurality of ports to route packets from a source port to one of several destination ports, wherein the packets are comprised of a command word containing information corresponding to packet routing, data format, size, and transaction identification;

transmitting data packets between a first device, a second device, and a third device coupled to the switching matrix as follows;

transmitting a first packet from the first device to the second or third device concurrently with;

transmitting a second packet from the second device to either the first device or the third device, concurrently with;

transmitting a third packet from the third device to either the first device or the third device;

wherein one of the data packets includes a virtual backplane bit.

20. The method of claim 19, wherein the command word includes a destination identification number for routing the packet to a destination device, a source identification number used by a destination device to send back responses, a transaction number to tag requests that require a response, and a packet type value indicating a particular type of packet.

21. The method of claim 19, wherein one of the data packets includes a bit that indicates a coherent transaction, a bit to guarantee bandwidth, an error bit which indicates whether an error occurred during transmission, and a bit that is used as a sync barrier for write ordering.

22. The method of claim 19, wherein the packets correspond to a fetch and operation packet with increment by one, a fetch and operation packet with decrement by one, a fetch and operation packet with clear, a store and operation packet with increment by one, a store and operation packet with decrement by one, a store and operation packet with a logical OR, and a store and operation packet with a logical AND.

23. The method of claim 19, wherein one of the packets includes sideband bits that are used to transfer information between sending and receiving devices.