Method and apparatus for processing a received signal in a communications system
First Claim
1. A receiver unit, comprising:
- a first buffer operative to receive and store digitized samples comprising multiple instances of a received signal;
a data processor coupled to the first buffer and operative to (a) retrieve different segments of the digitized samples one segment at a time from the first buffer, each of the retrieved different segments comprising one of the multiple signal instances, (b) process two or more of the retrieved different segments one segment at a time with one programmed despreading sequence to provide despread samples, (c) decover the despread samples with a channelization code of programmable length to provide decovered symbols, (d) demodulate the decovered symbols to provide demodulated symbols, and (e) combine the demodulated symbols from the multiple signal instances to provide processed symbols;
a controller being operative to direct the data processor;
a microcontroller coupled to the data processor and the controller, the microcontroller being operative to receive tasks from the controller, instantiate a state machine for each task, and direct the data processor to process the retrieved different segments; and
an address generator coupled to the first buffer and the controller, the address generator being operative to implement a counter to control a write address for writing digitized samples to the first buffer, the counter being operative to send a signal to the controller to initiate processing of the stored samples by the data processor.
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Abstract
A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameter values. The data processor is operated based on a processing clock having a frequency that is (e.g., ten or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer. The receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.
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Citations
51 Claims
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1. A receiver unit, comprising:
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a first buffer operative to receive and store digitized samples comprising multiple instances of a received signal; a data processor coupled to the first buffer and operative to (a) retrieve different segments of the digitized samples one segment at a time from the first buffer, each of the retrieved different segments comprising one of the multiple signal instances, (b) process two or more of the retrieved different segments one segment at a time with one programmed despreading sequence to provide despread samples, (c) decover the despread samples with a channelization code of programmable length to provide decovered symbols, (d) demodulate the decovered symbols to provide demodulated symbols, and (e) combine the demodulated symbols from the multiple signal instances to provide processed symbols; a controller being operative to direct the data processor; a microcontroller coupled to the data processor and the controller, the microcontroller being operative to receive tasks from the controller, instantiate a state machine for each task, and direct the data processor to process the retrieved different segments; and an address generator coupled to the first buffer and the controller, the address generator being operative to implement a counter to control a write address for writing digitized samples to the first buffer, the counter being operative to send a signal to the controller to initiate processing of the stored samples by the data processor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A receiver unit, comprising:
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a first buffer operative to receive and store digitized samples at a particular sample rate; and a data processor coupled to the first buffer and operative to retrieve segments of the digitized samples from the first buffer and to process the retrieved segments with a particular set of parameter values, wherein the data processor is operated based on a processing clock having a frequency that is higher than the sample rate, and wherein the data processor includes a correlator operative to despread the retrieved segments of the digitized samples with corresponding segments of PN (pseudo-random noise) despreading sequences to provide correlated samples, the correlator including an interpolator operative to receive and interpolate the despread samples to generate interpolated samples that are provided as the correlated samples, and wherein the interpolator includes one or more pairs of scaling elements, each of the scaling elements operative to receive and scale respective despread samples with a particular gain to generate scaled samples, and one or more summer, each of the summers coupled to a respective pair of scaling elements and operative to receive and sum the scaled samples from the pair of scaling elements to generate the interpolated samples.
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9. A receiver unit, in a wireless communications system, comprising:
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a first buffer operative to receive and store digitized samples at a particular sample rate; a data processor coupled to the first buffer and operative to retrieve segments of the digitized samples from the first buffer and to process each of the retrieved segments with a particular set of parameter values, wherein the data processor is operated based on a processing clock having a frequency that is higher than the sample rate; a controller coupled to the data processor and operative to dispatch tasks for the data processor and to process signaling data from the data processor; and a micro-controller coupled to the controller and operative to receive the dispatched tasks and to generate a set of control signals to direct the operation of the first buffer and the data processor to execute the dispatched tasks, wherein the micro-controller includes a set of latches operative to latch a dispatched task and one or more parameter values to be applied for the dispatched task, at least one counter, each of the counters coupled to a respective latch and operative to provide an indicator signal based on a value stored in the latch, and a sequencing controller operative to receive at least one indicator signal and the dispatched task and to generate the set of control signals. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
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44. A method for processing a received signal in a wireless communications system, the method comprising:
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buffering digitized samples of a received signal in a first buffer; retrieving segments of the digitized samples from the first buffer, processing each of the retrieved segments with a particular set of parameter values; dispatching tasks for a data processor to process the retrieved segments and to process signaling data from the data processor; receiving the dispatched tasks and generating a set of control signals to direct the operation of the first buffer and the data processor to execute the dispatched tasks; latching a dispatched task and one or more parameter values to be applied for the dispatched task; providing an indicator signal based on a value stored in the latch; and receiving at least one indicator signal and the dispatched task and to generate the set of control signals. - View Dependent Claims (45, 46, 47, 48, 49, 50)
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51. A method comprising:
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storing digitized samples comprising multiple instances of a received signal at a first buffer; at a data processor, retrieving different segments of the digitized samples one segment at a time from the first buffer, each of the retrieved different segments comprising one of the multiple signal instances; processing two or more of the retrieved different segments one segment at a time with one programmed despreading sequence to provide despread samples; decovering the despread samples with a channelization code of programmable length to provide decovered symbols; demodulating the decovered symbols to provide demodulated symbols; combining the demodulated symbols from the multiple signal instances to provide processed symbols; receiving tasks, instantiating a state machine for each task, and directing the data processor to process the retrieved multiple segments; implementing a counter to control a write address for writing digitized samples to the first buffer; and sending a signal to a controller to initiate processing of the stored samples by the data processor.
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Specification