Direct current offset cancellation for mobile station modems using direct conversion

• US 6,985,711 B2
• Filed: 05/02/2002
• Issued: 01/10/2006
• Est. Priority Date: 04/09/2002
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kang, Inyup, Holenstein, Christian, Severson, Matthew
• Primary Examiner(s): VO, NGUYEN THANH
• Application Number:
  US10/139,205
• Publication Number:
  US 20030199264A1
• Time in Patent Office: 1,349 Days
• Field of Search: 455/266, 455/296, 455/307, 455/324, 455/339, 455/340, 455/303, 455/311, 455/312, 375/346, 375/350
• US Class Current: 455/312
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A system and method for canceling DC offset for Mobile Station Modems having direct conversion architectures. The present invention is a fast acquiring DC offset cancellation block that provides rapid and accurate DC offset estimates and cancellation techniques to support direct conversion architectures. The fast acquiring DC offset cancellation block combines four mechanisms to rapidly acquire and remove a DC offset estimate after power up, temperature changes, receiver frequency changes, and gain setting changes by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. After removing the DC offset in large portions, the high pass loop bandwidth is decreased to fine tune the previous estimate and to remove any small variation in DC offset due to receiver self-mixing products.

Claims

1. A DC offset cancellation block in an RF receiver having a direct converter for direct down conversion of a received RF signal to a baseband signal, said DC offset cancellation block comprising:

offset adjustment means for removing static DC components from said baseband signal;

a coarse-grain loop for removing large portions of said static DC components and time-varying DC components from said baseband signal;

a fine-grain loop for removing said static and said time varying DC components from said baseband signal; and

a digital-to-analog converter controller (DACC) for removing large portions of said static DC components and slowly time-varying DC components by means of updating a digital-to-analog converter in said direct converter with a DC offset based on gain setting, receive frequency changes, and temperature changes of a low noise amplifier (LNA), a mixer, a baseband filter and an analog-to-digital converter (ADC) from a front end of said RF receiver;

wherein said offset adjustment means, said coarse-grain loop, said fine-grain loop, and said DACC interact with one another to remove unwanted DC offsets in said RF receiver.

2. The DC offset cancellation block of claim 1, wherein said offset adjustment means comprises a register and an adder, wherein said register stores an estimate of the static DC offset component and wherein said offset adjustment means subtracts the static DC offset component from said baseband signal.

3. The DC offset cancellation block of claim 1, wherein said coarse-grain loop comprises a gain element for enabling one of a high gain adjustment and a low gain adjustment, said high gun adjustment for expanding the bandwidth of a high pass filter to acquire the DC offset component, said low gain adjustment for narrowing the bandwidth of said high pass filter to track the DC offset component;

and an accumulator for accumulating the DC offset component.

4. The DC offset cancellation block of claim 3, wherein the 3 dB frequency of said high pass filter is increased when a gain change occurs in the front end of said RF receiver.

5. The DC offset cancellation block of claim 3, wherein the 3 dB frequency of said high pass filter is decreased when the DC offset component is locked in during tracking of the DC offset component.

6. The DC offset cancellation block of claim 3, wherein said coarse-grain loop further comprises a pulse density modulator (PDM) and an RC network which together form a digital-to-analog convener, for converting a digitized version of the DC offset component to an analog signal, wherein said analog signal is sent to said direct converter or said ADC to remove the DC offset component from said baseband signal.

7. The DC offset cancellation block of claim 1, wherein said fine-gain loop comprises a gain element for enabling one of a high gain adjustment and a low gain adjustment, said high gain adjustment for expanding the bandwidth of a high pass filter to acquire the DC offset component, said low gain adjustment for narrowing the bandwidth of said high pass filter to track the DC offset component;

an accumulator for accumulating the DC offset component; and

an adder for subtracting the accumulated DC offset component from said baseband signal.

8. The DC offset cancellation block of claim 7, wherein said fine-grain loop operates in a digital domain.

9. The DC offset cancellation block of claim 1, wherein said DACC comprises an estimator for determining an estimate of the DC offset, a multiplier for scaling the DC offset obtained from said animator, and a plurality of accumulators, wherein each of said plurality of accumulators determines a DC offset value based on said gain setting and temperature changes of said low noise amplifier (LNA) and said mixer from said front end of said RF receiver, wherein said plurality of accumulators accept as input one of the DC offset from said estimator and the DC offset from another DC estimator.

10. The DC offset cancellation block of claim 9, wherein the DC offset determined from said estimator is used to update said DAC in said direct converter when the DC offset is greater than a threshold value.

11. The DC offset cancellation block of claim 9, wherein said DACC further comprises a timer, wherein said DACC periodically updates said DAC in said direct converter with the DC offset generated by one of said plurality of accumulators when said timer times-out.

12. The DC offset cancellation block of claim 9, wherein said one of said plurality of accumulators is determined by the gain setting of said LNA and said mixer of said front end of said receiver.

13. The DC offset cancellation block of claim 9, wherein said estimator comprises a gain element for enabling one of a high gain adjustment and a low gain adjustment, said high gain adjustment for expanding the bandwidth of a high pass filter to acquire the DC offset component said low gain adjustment for narrowing the bandwidth of said high pass filter to track the DC offset component;

an accumulator for accumulating the DC offset component; and

an adder for subtracting the accumulated DC offset component from said baseband signal.

14. A method for cancelling DC offset in an RF receiver having a direct converter for direct down conversion of a received RF signal to a baseband signal, said method comprising the steps of:

(1) applying a high gain to expand the bandwidth of a high pass filter when a gain change occurs in said RF receiver;

(2) rapidly acquiring the DC offset within said baseband signal prior to the timing out of a timer;

(3) applying a low gain to narrow the bandwidth of said high pass filter when the timer has timed-out; and

(4) tracking the DC offset to fine tune the acquired DC offset, wherein the DC offset is removed from the baseband signal.

15. The method of claim 14, wherein a static DC offset is removed from said baseband signal prior to performing step (1) to prevent saturation of said RF receiver.

16. The method of claim 14, further comprising the steps of:

(5) storing in accumulators a DC offset estimate for each gain swing in the RF receiver based on the acquired DC offset from step (4); and

(6) updating a digital-to-analog converter in said direct converter using one of the DC offset estimates stored in accumulators, said one of the DC offset estimates being determined by said gain setting in use by said RF receiver.

17. The method of claim 14, further comprising the steps of:

(5) adding a estimated DC offset from step (4) to current DC offset estimates stored in accumulators for each gain setting;

(6) storing the resultant estimated DC offsets from step (5) in said accumulators for each gain setting; and

(7) updating a digital-to-analog converter in said direct converter using one of said DC offset estimates stored in said accumulators, said one of said DC offset estimates being determined by said gain setting in use by said RF receiver.

18. The method of claim 17, wherein steps (5)–

(7) are performed whenever the DC offset of a fine grain loop exceeds a programmable threshold value.

19. The method of claim 17, wherein steps (5)–

(7) are performed periodically based on a timer timing-out.

20. The method of claim 17, further comprising the steps of:

(8) updating said accumulators with correct DC offset value; and

(9) updating a digital-to-analog converter in said direct converter when a temperature change has occurred.

21. The method of claim 20, wherein step (8) comprises the steps of:

(a) reading the DC offsets from said accumulators;

(b) staring the DC offsets in an old temperature setting;

(c) reading new DC offset values from memory fur the new temperature setting; and

(d) overwriting said accumulators with the new DC offset values with the exception of the DC offset of said one of said accumulators associated with the current gain setting of said RF receiver and using said one of said accumulators to update said digital-to-analog converter in said direct converter.

22. A DC offset cancellation block;

comprising;

offset adjustment means for removing static DC components from a baseband signal;

a coarse-grain loop for removing large portions of said static DC components and time-varying DC components from said baseband signal;

a fine-grain loop fur removing said static and time-varying DC components from said baseband signal; and

a digital-to-analog converter controller (DACC) for removing large portions of said static DC components and slowly time-varying DC components by means of updating a digital-to-analog converter with a DC offset based on gain setting changes, frequency changes, and temperature changes of an amplifier and a mixer from a front end of a receiver.

23. The DC offset cancellation block of claim 22, wherein said offset adjustment means, said coarse-grain loop, said fine-grain loop, and said DACC interact with one another to remove unwanted DC offset in said receiver.