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Conductor arrangement for reduced noise differential signalling

  • US 6,985,820 B2
  • Filed: 03/19/2004
  • Issued: 01/10/2006
  • Est. Priority Date: 03/19/2004
  • Status: Active Grant
First Claim
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1. A method for analyzing input output (I/O) pin arrangements to determine the effect of differential pair and power and ground pin placement on signal quality comprising:

  • constructing an array of pins;

    arranging a plurality of differential pairs within the array of pins to provide a pin arrangement;

    exciting each of the differential pairs within the pin arrangement;

    monitoring coupled noise on other differential pairs within the pin arrangement;

    analyzing the pin arrangement based upon the monitoring, the analyzing the pin arrangement includinggenerating a coupling plot based upon the monitoring; and

    determining cumulative coupling based upon the coupling plot.

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