Conductor arrangement for reduced noise differential signalling
First Claim
Patent Images
1. A method for analyzing input output (I/O) pin arrangements to determine the effect of differential pair and power and ground pin placement on signal quality comprising:
- constructing an array of pins;
arranging a plurality of differential pairs within the array of pins to provide a pin arrangement;
exciting each of the differential pairs within the pin arrangement;
monitoring coupled noise on other differential pairs within the pin arrangement;
analyzing the pin arrangement based upon the monitoring, the analyzing the pin arrangement includinggenerating a coupling plot based upon the monitoring; and
determining cumulative coupling based upon the coupling plot.
2 Assignments
0 Petitions
Accused Products
Abstract
A method for analyzing input output (I/O) pin arrangements to determine the effect of differential pair and power and ground pin placement on signal quality which includes constructing an array of pins, arranging a plurality of differential pairs within the array of pins to provide a pin arrangement, exciting each of the differential pairs within the pin arrangement, monitoring coupled noise on other differential pairs within the pin arrangement, and analyzing the pin arrangement based upon the monitoring.
7 Citations
18 Claims
-
1. A method for analyzing input output (I/O) pin arrangements to determine the effect of differential pair and power and ground pin placement on signal quality comprising:
-
constructing an array of pins; arranging a plurality of differential pairs within the array of pins to provide a pin arrangement; exciting each of the differential pairs within the pin arrangement; monitoring coupled noise on other differential pairs within the pin arrangement; analyzing the pin arrangement based upon the monitoring, the analyzing the pin arrangement including generating a coupling plot based upon the monitoring; and determining cumulative coupling based upon the coupling plot. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. An apparatus for analyzing input output (I/O) pin arrangements to determine the effect of differential pair and power and ground pin placement on signal quality comprising:
-
means for constructing an array of pins; means for arranging a plurality of differential pairs within the array of pins to provide a pin arrangement; means for exciting each of the differential pairs within the pin arrangement; means for monitoring coupled noise on other differential pairs within the pin arrangement; means for analyzing the pin arrangement based upon the monitoring, the means for analyzing the pin arrangement including means for generating a coupling plot based upon the monitoring; and means for determining cumulative coupling based upon the coupling plot. - View Dependent Claims (8, 9, 10, 11, 12)
-
-
13. An apparatus comprising:
-
a processor; a memory coupled to the processor; and a system for analyzing input output (I/O) pin arrangements to determine the effect of differential pair and power and ground pin placement on signal quality, the system being stored on the memory and executing on the processor, the system including a constructing module, the constructing module constructing an array of pins; an arranging module, the arranging module arranging a plurality of differential pairs within the array of pins to provide a pin arrangement; an exciting module, the exciting module exciting each of the differential pairs within the pin arrangement; a monitoring module, the monitoring module monitoring coupled noise on other differential pairs within the pin arrangement; and
,an analyzing module, the analyzing module analyzing the pin arrangement based upon the monitoring the analyzing module including a generating module, the generating module generating a coupling plot based upon the monitoring; and a determining module, the determining module determining cumulative coupling based upon the coupling plot. - View Dependent Claims (14, 15, 16, 17, 18)
-
Specification