Cell modeling in the design of an integrated circuit

• US 6,985,843 B2
• Filed: 06/11/2001
• Issued: 01/10/2006
• Est. Priority Date: 06/11/2001
• Status: Expired due to Fees

• Current Assignee: NEC Electronics America Incorporated (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics America Incorporated (Renesas Electronics Corporation)
• Inventors: Kovacs-Birkas, Attila
• Primary Examiner(s): THOMSON, WILLIAM D
• Application Number:
  US09/878,497
• Publication Number:
  US 20020199155A1
• Time in Patent Office: 1,674 Days
• Field of Search: 703/13, 703/14, 703/15, 703/19, 703/20, 716/15, 716/8, 716/9, 716/6, 716/10, 716/2, 716/7, 716/11, 716/13, 716/17, 716/18
• US Class Current: 703/15
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is not available on the perimeter of the integrated circuit. The input/output cell can be modeled in two locations; one location on the perimeter of the cell and a second location in the interior area, or core, of the integrated circuit. The model uses a cover to prevent the area of the core of the integrated circuit from being used for other purposes. When the input/output cell is divided into a main cell and more than one pre-cell, the model uses a cover for each pre-cell. The model adjusts the timing of the signals to compensate for the input/output cell being divided into two areas. In an embodiment a software tool performs the functions of the model.

Claims

1. A computer program product, encoded in computer readable media, the computer program product for designing an integrated circuit chip, comprising:

a first set of instructions, executable on a computer system, the first set of instructions configured to model an input/output cell located on a perimeter of an integrated circuit, the model of the input/output cell comprising;

a model of a main cell; and

a model of a pre-cell; and

a second set of instructions, executable on the computer system, the second set of instructions configured to model a cover wherein the cover prevents an area occupied by the pre-cell from being used for any other purpose.

2. The computer program product as recited in claim 1, further comprising:

a third set of instructions, executable on the computer system, the third set of instructions configured to adjust signal timing of the main-cell and pre-cell models, wherein the signal timing adjustment to the main cell and pre-cell models approximates a signal timing of the input/output cell.

3. The computer program product as recited in claim 1,

wherein the model of input/out put cell comprises a second pre-cell;

wherein the second set of instructions are configured to model a second cover, wherein the second cover prevents an area occupied by the second pre-cell from being used for any other purpose.

4. The computer program product as recited in claim 1, the computer program product further comprising:

a database, wherein the database stores a netlist.

5. The computer program product as recited in claim 1, the computer program product further comprising:

a third set of instructions, executable on the computer system, the third set of instructions configured to convert a netlist to a proprietary format.

6. The computer program product as recited in claim 1, further comprising:

a third set of instructions, executable on the computer system, the third set of instructions configured to flatten a netlist by reading a description of a function of a cell and listing each function of the cell individual.

7. The computer program product as recited in claim 1, further comprising:

a third set of instructions, executable on the computer system, the third set of instructions configured to identify a location of each pin in an integrated circuit.

8. The computer program product as recited in claim 1, further comprising:

a third set of instructions, executable on the computer system, the third set of instructions configured to identify a location of each cell in an integrated circuit.

9. A method of modeling an input/output cell on a perimeter of an integrated circuit and at a location in a core area of the integrated circuit, the method comprising:

modeling the input/output cell, wherein the input/output cell model comprises;

a model of a main cell; and

a model of a pre-cell; and

modeling a cover wherein the cover prevents an area designated to be occupied by the model of the pre-cell from being used for any other purpose.

10. An integrated circuit manufactured by the method as recited in claim 9.

11. The method as recited in claim 9, further comprising:

adjusting a signal timing of the main-cell and pre-cell models, so that the signal timing of the main cell and the pre-cell models approximates a signal timing of input/output cell.

12. The method as recited in claim 9, further comprising:

modeling a second cover;

wherein the input/output cell comprises a second pre-cell model, wherein the first cover prevents use of the area of the first pre-cell and the second cover prevents use of the area covered by the second pre-cell;

wherein the second cover prevents an area designated to be occupied by the model of the second pre-cell from being used for any other purpose.

13. The method as recited in claim 9, further comprising:

storing a netlist.

14. The method as recited in claim 9, further comprising:

converting a netlist to a proprietary format.

15. The method as recited in claim 9, further comprising:

listing each function of a cell individually.

16. The method as recited in claim 9, further comprising:

identifying a location of each pin in the integrated circuit.

17. The method as recited in claim 9, further comprising:

identifying a location of each cell in the integrated circuit.

18. A computer system, comprising:

a memory; and

a central processing unit, wherein the central processing unit is designed to execute instructions of a computer program stored in the memory, the computer program comprising;

a first set of instructions configured to model an input/output cell located on a perimeter of an integrated circuit;

the model of the input/output cell comprising;

a model of a main cell; and

a model of a first pre-cell; and

a second set of instructions configured to model a cover wherein the cover prevents an area occupied by the first pre-cell from being used for any other purpose.

19. The computer system as recited in claim 18 wherein the computer program further comprises:

a third set of instructions configured to adjust a signal timing of the main-cell and pre-cell models, so that the signal timing of the main cell and first pre-cell models approximates a signal timing of the input/output cell.

20. The computer system as recited in claim 18, wherein the computer program further comprises:

a third set of instructions configured to model a second cover;

wherein the input/output cell comprises a model a second pre-cell;

wherein the second cover prevents use of an area occupied by the second pre-cell from being used for any other purpose.

21. The computer system as recited in claim 18, further comprising:

a database, wherein the database stores a netlist.

22. The computer system as recited in claim 18 wherein the computer program further comprises:

a third set of instructions, the third set of instructions configured to convert a netlist to a proprietary format.

23. The computer system as recited in claim 18 wherein the computer program further comprises:

a third set of instructions, the third set of instructions configured to read a description of a function of a cell and list each function of the cell individually, wherein reading the description of the function of the cell and listing each function of the cell individually is referred to as flattening a netlist.