System-on-a-Chip structure having a multiple channel bus bridge

• US 6,985,988 B1
• Filed: 11/09/2000
• Issued: 01/10/2006
• Est. Priority Date: 11/09/2000
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Nsame, Pascal A.
• Primary Examiner(s): Vo, Tim
• Assistant Examiner(s): Huynh, Kim T.
• Application Number:
  US09/708,494
• Time in Patent Office: 1,888 Days
• Field of Search: 710/100, 710/306, 710/305, 710240-244, 710/4, 714/30
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A system-on-a-chip integrated circuit structure includes a bridge having a plurality of channels, a processor local bus connected to the bridge (wherein the bridge includes a first channel dedicated to the processor local bus), at least one logic device connected to the processor local bus, a peripheral device bus connected to the bridge (wherein the bridge includes a second channel dedicated to the peripheral device bus), at least one peripheral device connected to the peripheral device bus, at least one memory unit connected to the bridge (wherein the bridge includes a third channel dedicated to the memory unit), and at least one input/output unit connected to the bridge (wherein the bridge includes a fourth channel dedicated to the input/output unit).

Claims

1. A system-on-a-chip integrated circuit structure comprising:

a bridge having a plurality of channels in said bridge;

a processor local bus connected to said bridge, wherein said bridge includes a first channel dedicated to said processor local bus;

at least one logic device connected to said processor local bus;

a peripheral device bus connected to said bridge, wherein said bridge includes a second channel dedicated to said peripheral device bus;

at least one peripheral device connected to said peripheral device bus;

at least one memory unit connected to said bridge, wherein said bridge includes a third channel dedicated to said memory unit; and

at least one input/output unit connected to said bridge, wherein said bridge includes a fourth channel dedicated to said input/output unit.

2. The structure in claim 1, wherein each of said channels includes buffer memories adapted to store data when a previous data transfer is being performed.

3. The structure in claim 2, wherein said buffer memories comprise first-in first-out buffer memories.

4. The structure in claim 1, wherein each of said channels includes a multi-port static random access memory (SRAM) adapted to store data when a previous data transfer is being performed.

5. The structure in claim 1, wherein each of said channels includes a multiplexor adapted to selectively connect to other channels.

6. The structure in claim 1, wherein said at least one memory unit comprises a first-type memory unit and a second-type memory unit different than said first-type memory unit, wherein said third channel is dedicated to said first-type memory unit and said bridge includes a fifth channel dedicated to said second-type memory unit.

7. The structure in claim 6, wherein said first-type memory unit comprises static random access memory (SRAM) and said second-type memory unit comprises synchronous dynamic random access memory (SDRAM).

8. The structure in claim 1, wherein said at least one input/output unit comprises one or more of a peripheral interface, graphics interface, and serial bus interface, and wherein said bridge includes dedicated channels for each of said peripheral interface, graphics interface, and serial bus interface.

9. The structure in claim 1, wherein said at least one peripheral device includes one or more of a serial connection, network interface connection, and programmable input/output connection each connected to said peripheral device bus.

10. A system-on-a-chip integrated circuit structure comprising:

A bridge having a plurality of channels;

At least one bus connected to a unique dedicated channel in said bridge;

At least one memory unit connected to a unique dedicated channel in said bridge; and

At least one input/output unit connected to a unique dedicated channel in said bridge;

Wherein said at least one bus includes;

A processor local bus connected to said bridge, wherein said bridge includes a first channel dedicated to said processor local bus; and

A peripheral device bus connected to said bridge, wherein said bridge includes a second channel dedicated to said peripheral device bus, wherein said structure further comprises;

at least one logic device connected to said processor local bus; and

at least one peripheral device connected to said peripheral device bus.

11. The structure in claim 10, wherein each of said channels includes buffer memories adapted to store data when a previous data transfer is being performed.

12. The structure in claim 11, wherein said buffer memories comprise first-in first-out buffer memories.

13. The structure in claim 10, wherein each of said channels includes a multi-port static random access memory (SRAM) adapted to store data when a previous data transfer is being performed.

14. The structure in claim 10, wherein each of said channels includes a multiplexor adapted to selectively connect to other channels.

15. The structure in claim 10, wherein said at least one memory unit comprises a first-type memory unit and a second-type memory unit different than said first-type memory unit, wherein said bridge includes a first channel is dedicated to said first-type memory unit and a second channel dedicated to said second-type memory unit.

16. The structure in claim 15, wherein said first-type memory unit comprises static random access memory (SRAM) and said second-type memory unit comprises synchronous dynamic random access memory (SDRAM).

17. The structure in claim 10, wherein said at least one input/output unit comprises one or more of a peripheral interface, graphics interface, and serial bus interface, and wherein said bridge includes unique dedicated channels for each of said peripheral interface, graphics interface, and serial bus interface.

18. The structure in claim 10, wherein said at least one peripheral device includes one or more of a serial connection, network interface connection, and programmable input/output connection each connected to said peripheral device bus.

19. A bridge for a system-on-a-chip (SoC) integrated circuit structure comprising:

A plurality of dedicated channels in said bridge each uniquely connected to one or more of;

At least one bus within said SoC;

At least one memory unit within said SoC;

At least one input/output unit within said SoC; and

At least one peripheral device within said SoC;

Wherein said at least one bus includes;

A processor local bus connected to said bridge, wherein said bridge includes a first channel dedicated to said processor local bus; and

A peripheral device bus connected to said bridge, wherein said bridge includes a second channel dedicated to said peripheral device bus, wherein said SoC includes;

At least one logic device connected to said processor local bus; and

At least one peripheral device connected to said peripheral device bus.

20. The structure in claim 19, wherein each of said channels includes buffer memories adapted to store data when a previous data transfer is being performed.

21. The structure in claim 20, wherein said buffer memories comprise first-in first-out buffer memories.

22. The structure in claim 19, wherein each of said channels includes a multi-port static random access memory (SRAM) adapted to store data when a previous data transfer is being performed.

23. The structure in claim 19, wherein each of said channels includes a multiplexor adapted to selectively connect to other channels.

24. The structure in claim 19, wherein said at least one memory unit comprises a first-type memory unit and a second-type memory unit different than said first-type memory unit, wherein said bridge includes a first channel is dedicated to said first-type memory unit and a second channel dedicated to said second-type memory unit.

25. The structure in claim 24, wherein said first-type memory unit comprises static random access memory (SRAM) and said second-type memory unit comprises synchronous dynamic random access memory (SDRAM).

26. The structure in claim 19, wherein said at least one input/output unit comprises one or more of a peripheral interface, graphics interface, and serial bus interface, and wherein said bridge includes unique dedicated charnels for each of said peripheral interface, graphics interface, and serial bus interface.

27. The structure in claim 19, wherein said at least one peripheral device includes one or more of a serial connection, network interface connection, and programmable input/output connection each connected to said peripheral device bus.