Boundary synchronization mechanism for a processor of a systolic array

• US 6,986,022 B1
• Filed: 10/16/2001
• Issued: 01/10/2006
• Est. Priority Date: 10/16/2001
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Kerr, Darren, Marshall, John William, Burns, Barry S.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/978,640
• Time in Patent Office: 1,547 Days
• Field of Search: 712/19, 712/13, 712/22, 712/221, 708/493, 708/622, 713/375
• US Class Current: 712/19
• CPC Class Codes: G06F 15/8046 Systolic arrays

Abstract

A mechanism synchronizes instruction code executing on a processor of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a boundary (temporal) synchronization mechanism for cycle-based synchronization within a processor of the array. The synchronization mechanism is generally implemented using specialized synchronization micro operation codes (“opcodes”).

Claims

1. A system for synchronizing instruction code executed by a processor of a processing engine in an intermediate network station, the processing engine configured as a systolic array having a plurality of processors arrayed as rows and columns, each processor of a column executing similar instruction code, the system comprising:

a temporal synchronization mechanism associated with each processor of the array, the temporal synchronization mechanism including boundary logic configured to specify an offset from one of a start of a phase and relative to a marker at which execution of an instruction may be delayed.

2. The system of claim 1 wherein the temporal synchronization mechanism provides cycle-based synchronization within the processor.

3. The system of claim 1 wherein the boundary logic comprises:

a count register of the processor, the count register containing a timer value indicating a number of clock cycles that have elapsed since the start of phase; and

a boundary reference threshold register containing a threshold value indicating an allowable duration for execution of a code sequence on the processor.

4. The system of claim 3 wherein the processor compares the timer value with the threshold value to determine whether further program instruction code execution can proceed without incurring stall cycles.

5. A system for synchronizing instruction code executed by a processor of a processing engine in an intermediate network station, the processing engine configured as a systolic array having a plurality of processors arrayed as rows and columns, each processor of a column executing similar instruction code, the system comprising:

a temporal synchronization mechanism associated with each processor of the array, the temporal synchronization mechanism including boundary logic configured to specify an offset from one of a start of a phase and relative to a marker at which execution of an instruction may be delayed;

boundary logic having a count register of the processor, the count register containing a timer value indicating a number of clock cycles that have elapsed since the start of phase;

a boundary reference threshold register containing a threshold value indicating an allowable duration for execution of a code sequence on the processor;

said each processor compares the timer value with the threshold value to determine whether further program instruction code execution can proceed without incurring stall cycles; and

a boundary reference (bref) instruction opcode that selectively resets the timer value to identify start of a new synchronization interval and that sets the threshold value used for comparison with the timer value.

6. The system of claim 5 wherein the bref opcode comprises an operand configured to select a specific boundary condition to thereby enable the temporal synchronization mechanism to support a plurality of boundary synchronization operations.

7. The system of claim 6 wherein the boundary logic is replicated in each processor.

8. A method for synchronizing instruction code executed by a processor of a processing engine in an intermediate network station, the processing engine configured as a systolic array having a plurality of processors arrayed as rows and columns, each processor of a column executing similar instruction code, the method comprising the steps of:

allowing execution of a code sequence on the processor for a minimum duration specified by a duration of a duration register;

if a code path executed by the processor completes before the specified duration, stalling the processor until the duration has elapsed; and

if a code path execution time is greater than or equal to the specified duration, continuing execution of the code sequence on the processor without incurring stall cycles.

9. A method for synchronizing instruction code executed by a processor of a processing engine in an intermediate network station, the processing engine configured as a systolic array having a plurality of processors arrayed as rows and columns, each processor of a column executing similar instruction code, the method comprising the steps of:

providing a synchronization operation code (opcode) adapted for execution by the processor;

interpreting the synchronization opcode based on a state of a predetermined bit of a machine state register within the processor; and

performing temporal synchronization when the predetermined bit is non-asserted.

10. The method of claim 9 wherein the step of performing comprises the steps of:

bounding a minimum execution latency through a section of the code;

identifying a start of the code section by one of a start of a software phase, a barrier event and an instruction-initiated, boundary reference opcode; and

identifying an end of the code section by a bsync opcode.

11. A method for synchronizing instruction code within a processor of a multiprocessor system configured as a systolic array, the array having a plurality of processors arrayed as rows and columns, each processor of a column executing similar instruction code, the method comprising the steps of:

initiating a cycle timer value responsive to the processor;

setting a threshold value to a specified number of cycles; and

suspending further execution of the instruction code until the timer value is greater than or equal to the threshold value.

12. The method of claim 11 further comprising the steps of:

resetting the timer value at a beginning of a phase; and

selectively resetting the timer value one or more times during the phase by executing a first instruction.

13. A method for synchronizing instruction code within a

processor of a multiprocessor system configured as a systolic array, the array having a plurality of processors arrayed as rows and columns, each processor of a column executing similar instruction code, the method comprising the steps of:

initiating a cycle timer value responsive to the processor;

setting a threshold value to a specified number of cycles;

suspending further execution of the instruction code until the timer value is greater than or equal to the threshold value;

resetting the timer value at a beginning of a phase;

selectively resetting the timer value one or more times during the phase by executing a first instruction;

setting the threshold value by executing a second instruction.

14. The method of claim 13 further comprising the step of inserting a micro-opcode within the instruction code to delay execution of the instruction code until a boundary event.

15. Apparatus adapted to synchronize instruction code within a processor of a multiprocessor system configured as a systolic array, the array having a plurality of processors arrayed as rows and columns, each processor of a column executing similar instruction code, the apparatus comprising:

means for initiating a cycle timer value responsive to the processor;

means for setting a threshold value to a specified number of cycles; and

means for suspending further execution of the instruction code until the timer value is greater than or equal to the threshold value.

16. Apparatus adapted to synchronize instruction code within a processor of a multiprocessor system configured as a systolic array, the array having a plurality of processors arrayed as rows and columns, each processor of a column executing similar instruction code, the apparatus comprising:

means for initiating a cycle timer value responsive to the processor;

means for setting a threshold value to a specified number of cycles;

means for suspending further execution of the instruction code until the timer value is greater than or equal to the threshold value;

means for resetting the timer value at a beginning of a phase; and

means for selectively resetting the timer value one or more times during the phase by executing a first instruction.

17. The apparatus of claim 16 wherein the step of setting the threshold value comprises setting the threshold value by executing a second instruction.

18. The apparatus of claim 17 further comprising means for inserting a micro-opcode within the instruction code to delay execution of the instruction code until a boundary event.

19. A computer readable medium containing executable program instructions for synchronizing instruction code executed by a processor of a processing engine in an intermediate network station, the processing engine configured as a systolic array having a plurality of processors arrayed as rows and columns, each processor of a column executing similar instruction code, the executable program instructions comprising program instructions for:

providing a synchronization operation code (opcode) adapted for execution by the processor;

interpreting the synchronization opcode based on a state of a predetermined bit of a machine state register within the processor; and

performing temporal synchronization when the predetermined bit is non-asserted.

20. The computer readable medium of claim 19 wherein the program instruction for performing comprises program instructions for:

bounding a minimum execution latency through a section of the code;

identifying a start of the code section by one of a start of a software phase, a barrier event and an instruction-initiated, boundary reference opcode; and

identifying an end of the code section by a bsync opcode.