High-performance, superscalar-based computer system with out-of-order instruction execution
First Claim
1. A microprocessor, comprising:
- prefetch control logic that fetches a plurality of instruction sets from an instruction store, each of said plurality of instruction sets comprising a plurality of instructions;
a branch decoder that decodes said plurality of instruction sets fetched by said prefetch control logic;
a first in first out (FIFO) buffer comprising a plurality of registers, each of said plurality of registers adapted to store one of said plurality of instruction sets decoded by said branch decoder and control data associated therewith, said control data including a stream indicator that indicates whether said associated instruction set corresponds to a first instruction stream or a second instruction stream, and a valid indicator;
buffer control logic that serially transfers each of said plurality of instruction sets and said associated control data from a top portion of said FIFO buffer to a bottom portion of said FIFO buffer; and
an execution unit adapted to execute instructions from instruction sets stored in said bottom portion of said FIFO buffer dependent on the state of said valid indicator associated with each of said instruction sets stored in said bottom portion oil said FIFO buffer;
wherein said execution unit executes a branch instruction and provides a result of said branch instruction to said buffer control logic, and, based on said result, said buffer control logic changes the state of either each valid indicator associated with each of said plurality of instruction sets stored in said FIFO buffer corresponding to said first instruction stream or each valid indicator associated with each of said plurality of instruction sets stored in said FIFO buffer corresponding to said second instruction stream.
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Abstract
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
115 Citations
24 Claims
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1. A microprocessor, comprising:
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prefetch control logic that fetches a plurality of instruction sets from an instruction store, each of said plurality of instruction sets comprising a plurality of instructions;
a branch decoder that decodes said plurality of instruction sets fetched by said prefetch control logic;
a first in first out (FIFO) buffer comprising a plurality of registers, each of said plurality of registers adapted to store one of said plurality of instruction sets decoded by said branch decoder and control data associated therewith, said control data including a stream indicator that indicates whether said associated instruction set corresponds to a first instruction stream or a second instruction stream, and a valid indicator;
buffer control logic that serially transfers each of said plurality of instruction sets and said associated control data from a top portion of said FIFO buffer to a bottom portion of said FIFO buffer; and
an execution unit adapted to execute instructions from instruction sets stored in said bottom portion of said FIFO buffer dependent on the state of said valid indicator associated with each of said instruction sets stored in said bottom portion oil said FIFO buffer;
wherein said execution unit executes a branch instruction and provides a result of said branch instruction to said buffer control logic, and, based on said result, said buffer control logic changes the state of either each valid indicator associated with each of said plurality of instruction sets stored in said FIFO buffer corresponding to said first instruction stream or each valid indicator associated with each of said plurality of instruction sets stored in said FIFO buffer corresponding to said second instruction stream. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A microprocessor, comprising:
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prefetch control logic that fetches a plurality of instructions at a time from an instruction store;
a branch decoder that decodes said plurality of instructions fetched by said prefetch control logic;
a buffer comprising a plurality of registers and configured for first in first out (FIFO) input, output and transfer of instructions, each of said plurality of registers adapted to store at least one of said instructions decoded by said branch decoder and control data associated therewith, said control data including a stream indicator that indicates whether an associated plurality of instructions corresponds to a first instruction stream or a second instruction stream, and a valid indicator;
buffer control logic that serially transfers said instructions and said associated control data within said buffer; and
an execution unit adapted to execute instructions dependent on the state of said valid indicator associated with each of said plurality of instructions;
wherein said execution unit executes a branch instruction and provides a result of said branch instruction to said buffer control logic, and, based on said result, said buffer control logic changes the state of either each valid indicator associated with each of said plurality of instructions stored in said buffer corresponding to said first instruction stream or each valid indicator associated with each of said plurality of instructions stored in said buffer corresponding to said second instruction stream. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification