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High-performance, superscalar-based computer system with out-of-order instruction execution

  • US 6,986,024 B2
  • Filed: 10/30/2002
  • Issued: 01/10/2006
  • Est. Priority Date: 07/08/1991
  • Status: Expired due to Fees
First Claim
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1. A microprocessor, comprising:

  • prefetch control logic that fetches a plurality of instruction sets from an instruction store, each of said plurality of instruction sets comprising a plurality of instructions;

    a branch decoder that decodes said plurality of instruction sets fetched by said prefetch control logic;

    a first in first out (FIFO) buffer comprising a plurality of registers, each of said plurality of registers adapted to store one of said plurality of instruction sets decoded by said branch decoder and control data associated therewith, said control data including a stream indicator that indicates whether said associated instruction set corresponds to a first instruction stream or a second instruction stream, and a valid indicator;

    buffer control logic that serially transfers each of said plurality of instruction sets and said associated control data from a top portion of said FIFO buffer to a bottom portion of said FIFO buffer; and

    an execution unit adapted to execute instructions from instruction sets stored in said bottom portion of said FIFO buffer dependent on the state of said valid indicator associated with each of said instruction sets stored in said bottom portion oil said FIFO buffer;

    wherein said execution unit executes a branch instruction and provides a result of said branch instruction to said buffer control logic, and, based on said result, said buffer control logic changes the state of either each valid indicator associated with each of said plurality of instruction sets stored in said FIFO buffer corresponding to said first instruction stream or each valid indicator associated with each of said plurality of instruction sets stored in said FIFO buffer corresponding to said second instruction stream.

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