Method and apparatus for secure execution using a secure memory partition

• US 6,986,052 B1
• Filed: 06/30/2000
• Issued: 01/10/2006
• Est. Priority Date: 06/30/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mittal, Millind
• Primary Examiner(s): Darrow, Justin T.
• Application Number:
  US09/608,439
• Time in Patent Office: 2,020 Days
• Field of Search: 713/190, 713/188, 713/189, 713/193, 711/163
• US Class Current: 713/190
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 21/60 Protecting data
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G06F 2221/2125 Just-in-time application of countermeasures, e.g., on-the-fly decryption, just-in-time obfuscation or de-obfuscation

Abstract

A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Claims

1. An apparatus, comprising:

an execution unit that is part of a processor;

secure partition enforcement logic coupled to the execution unit, wherein the secure partition enforcement logic is part of the processor; and

a cryptographic logic element coupled to the execution unit, wherein the cryptographic logic is part of the processor.

2. The apparatus of claim 1, wherein the processor further comprises a plurality of secure partition registers.

3. The apparatus of claim 2, wherein the secure partition registers include a partition entry point register.

4. The apparatus of claim 3, wherein the processor further comprises a translation lookaside buffer coupled to the cryptographic logic element, and wherein the secure partition enforcement logic is coupled between the execution unit and the translation lookaside buffer.

5. A computer system, comprising:

a first memory; and

a processor that is coupled to the first memory and includes secure partition enforcement logic to establish a partition of virtual memory locations.

6. The computer system of claim 5, wherein the processor also includes a cryptographic logic element.

7. The computer system of claim 6, wherein the computer system further comprises a non-volatile memory, and wherein the secure partition enforcement logic further establishes a secure partition of memory locations in the non-volatile memory.

8. The computer system of claim 6, wherein the non-volatile memory stores verification enforcement instructions, and wherein the processor further includes bootstrap security logic to verify the authenticity of the verification enforcement instructions.

9. The computer system of claim 6, wherein the processor further includes a partition entry point register to store a partition entry point in the first memory.

10. A method of processing an instruction, comprising:

examining an instruction prior to execution of the instruction; and

determining to not execute the instruction when the instruction is an unauthorized access to a location within a partition of locations in virtual memory.

11. The method of claim 10, wherein said determining to not execute the instruction further includes trapping to a trap handler.

12. The method of claim 10, wherein the instruction is an unauthorized access when the instruction operates on data in a location within the partition and the instruction is not stored within the partition.

13. The method of claim 10, wherein the instruction is an unauthorized access when the instruction is a branch from a location outside the partition, the branch is to a location within the partition, and the branch is not to a partition entry point.

14. The method of claim 13, wherein the instruction is also an unauthorized access when the instruction is not stored at a partition entry point and the previous instruction executed was the instruction immediately before the beginning of the partition.

15. The method of claim 14, wherein the method further comprises:

executing the instruction when the instruction branches to a location within the partition from another location within the partition; and

executing the instruction when the instruction branches to a partition entry point from a location outside the partition.

16. A method of processing an instruction, the method comprising:

reading an encrypted instruction into a processor from a secure partition in a memory;

decrypting the instruction read; and

executing the decrypted instruction.

17. The method of claim 16, wherein executing the decrypted instruction includes:

determining whether the instruction is an instruction that reads data from the secure partition; and

reading the data from the secure partition and decrypting the data read if the instruction is an instruction that reads data from the secure partition.

18. The method of claim 17, wherein said determining whether the instruction is an instruction that reads data from the secure partition includes comparing the virtual address of the data with secure partition boundaries.

19. The method of claim 16, wherein executing the decrypted instruction includes:

determining whether the instruction is an instruction that writes data into a location in the secure partition; and

encrypting the data and writing the data to the location in the secure partition if the instruction is an instruction that writes data into the secure partition.