System and method for a family of digital subscriber line (XDSL) signal processing circuit operating with an internal clock rate that is higher than all communications ports operating with a plurality of port sampling clock rates

• US 6,986,073 B2
• Filed: 03/01/2001
• Issued: 01/10/2006
• Est. Priority Date: 03/01/2000
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Liu, Ming-Kang
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Suryawanshi, Suresh
• Application Number:
  US09/797,789
• Publication Number:
  US 20010037471A1
• Time in Patent Office: 1,776 Days
• Field of Search: 713/600, 713/500, 370/385.1, 370/468, 370/540, 370/538, 375/222
• US Class Current: 713/600
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 12/2856 Access arrangements, e.g. Internet access asynchronous transfer mode networks H04L12/5601; broadband local area networks H04L12/2801; optical access or distribution networks H04Q11/0067; access to open networks H04L12/5691; digital subscriber line end-user equipment and bit-level processing of data on a PSTN-based network H04M11/00; home network gateways H04L12/2834; wireless access networks H04W
• CPC Class Codes: H04L 12/289 Single service
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/6478 Digital subscriber line, e.g. DSL, ADSL, HDSL, XDSL, VDSL
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04M 11/062 using different frequency bands for speech and other data
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A communications system operates with an internal pipeline clock rate that is higher than that of any port used in the system. In an xDSL environment, this rate is higher than a DMT symbol rate used in the channel. In this manner, communications for the various ports can be synchronized and pipelined for transmit/receive operations. In addition, the higher rate results in idle processing periods, during which stuffing symbols are generate to maintain synchronism and/or pass along control information. The internal pipeline clock rate is selected to be higher than rate that may be encountered as well during an initialization routine and normal transmissions. The pipeline clock is also programmable so as to permit power management of the system.

Claims

1. A system for processing a family of digital subscriber line (xDSL) communications comprising:

a plurality of individual communications ports operating with a plurality of unique port sampling clock rates during a normal data transmission with a plurality of remote transceivers;

an xDSL signal processing circuit for performing signal processing operations for all of said plurality of individual communication ports, said xDSL signal processing circuit operating with an internal clock rate that is higher than any of said plurality of unique port clock sampling rates.

2. The system of claim 1, wherein each communication port of said plurality of individual communications ports is adapted to communicate using a first clock rate during initialization of a normal data transmission and using a second clock rate during a normal data transmission, where said second clock rate is greater than said first clock rate.

3. The system of claim 1, wherein said xDSL signal processing circuit is comprised of a logical pipeline with a plurality of individual stages, such that said plurality of individual stages each perform a discrete multi-tone (DMT) symbol related operation.

4. The system of claim 3, wherein said logical pipeline is a logical hybrid pipeline of a combination of hardware and software stages, arranged such that an output from a hardware stage is processed by an immediately following software stage in the logical hybrid pipeline and/or such that an output from a software stage is processed by an immediately following hardware stage in the logical hybrid pipeline.

5. The system of claim 1, wherein a nominal target clock rate frequency for said associated port sampling clock rate is approximately 4 kHz, and said internal clock rate is approximately 4 kHz*(N/N−

X) where N<

=69 and X>

=2.

6. A digital subscriber line (xDSL) processing pipeline for processing a family of xDSL communications based on discrete multi-tone (DMT) symbols transmitted and received through a channel during a data transmission at a first DMT symbol rate T for a plurality of individual ports, the pipeline comprising:

a plurality of individual pipeline stages, each of said individual stages being adapted for performing a processing operation associated with an xDSL communications link for one or more of the plurality of individual ports;

a pipeline clock for clocking said plurality of individual pipeline stages, said pipeline clock operating at a rate equal to the first DMT symbol rate multiplied by a constant greater than one, so that said pipeline operates at a rate faster than said first DMT symbol rate T.

7. The processing pipeline of claim 6, wherein the first DMT symbol rate in the channel is reduced during an initialization period before the data transmission begins.

8. The processing pipeline of claim 6, wherein a first number of DMT symbols received within a first processing period by the processing pipeline are processed during a second period that is shorter than said first period by a stuffing time interval equal to a period required to process a predetermined number of DMT symbols at said first DMT symbol rate T.

9. The processing pipeline of claim 8 wherein the processing pipeline processes a number of dummy DMT symbols equal to said predetermined number of DMT symbol during said stuffing time interval.

10. A system for processing a family of digital subscriber line (xDSL) communications involving discrete multi-tone (DMT) symbols transmitted and received through a channel during a normal data transmission at a nominal sampling clock rate, the system comprising:

a plurality of individual communications ports, each of said plurality of individual communications ports having an associated port sampling clock rate that can vary from the nominal DMT symbol rate, such that a plurality of port operational sampling clock rates are possible during the normal data transmission;

wherein said plurality of port operational sampling clock rates can also vary from each other so as to cause each of said plurality of individual communications ports to be asynchronous with respect to other of said plurality of individual communications ports;

a pipeline for performing processing operations for said plurality of individual communication ports, said pipeline operating with a pipeline clock at a pipeline clock rate that is higher than the nominal sampling clock rate and higher than any of said plurality of port operational sampling clock rates so that said plurality of individual communications ports can be processed in a synchronous manner.

11. The system of claim 10, wherein said pipeline is a hybrid combination of software and hardware components.

12. The system of claim 10, wherein all processing operations for a physical layer and a logical layer of said plurality of individual communications port are performed in said pipeline.

13. The system of claim 12, wherein said pipeline is coupled to an analog front end circuit coder/decoder (CODEC) and said CODEC operates with a CODEC clock using a CODEC clock rate substantially higher than said pipeline clock rate.

14. The system of claim 13, wherein said pipeline clock can be disabled and/or modified independently of said CODEC clock for some or all portions of said pipeline so as to reduce power consumption.

15. A system for processing a family of digital subscriber line (xDSL) communications involving discrete multi-tone (DMT) symbols transmitted and received through a channel during a normal data transmission at a nominal DMT symbol rate T, the system comprising:

a plurality of individual communications ports, each of said plurality of individual communications ports using a continuous sequence of DMT symbols for communicating data; and

a pipeline for performing processing operations during a processing interval on said continuous sequence of DMT symbols for said plurality of individual communication ports, said pipeline having a plurality of pipeline stages that operate within said processing interval at a pipeline clock rate that is higher than the nominal DMT symbol rate; and

said pipeline being further configured so that it supports one or more idle processing intervals, said idle processing intervals consisting of processing intervals during which processing operations for one or more of said individual communication ports is skipped.

16. The system of claim 15, wherein during said idle processing intervals said pipeline generates a stuffing symbol, said stuffing symbol including dummy data set up in a pipeline buffer for processing by one of said plurality of pipeline stages.

17. The system of claim 16, wherein said dummy data includes an indicator bit identifying a DMT symbol as a stuffing symbol so that software and hardware task blocks making up said pipeline stages will skip any operations normally performed on such DMT symbols.

18. The system of claim 15, wherein a sufficient number of said idle processing intervals are set up by the system so that operations for all of said plurality of individual communication ports can be synchronized to said pipeline clock rate.

19. The system of claim 15, wherein said nominal DMT symbol rate is based on a nominal rate specified by an asymmetric digital subscriber line (ADSL), single pair high-speed digital subscriber line (SHDSL) and/or very high data rate digital subscriber line (VDSL) standard.

20. A method of processing a family of digital subscriber line (xDSL) communications within a multi-port communication system comprising the steps of:

operating a plurality of individual communications ports with a plurality of port sampling clock rates during a normal data transmission with a plurality of remote transceivers; and

performing signal processing operations for all of said plurality of individual communication ports with an internal clock rate that is higher than any of said plurality of port sampling clock rates.

21. The method of claim 20, wherein each communication port of said plurality of individual communications ports is adapted to communicate using a first sampling clock rate during initialization of a normal data transmission and using a second sampling clock rate during a normal data transmission, where said second sampling clock rate is greater than said first sampling clock rate.

22. The method of claim 20 further including a step of performing said signal processing operations using a plurality of individual pipeline stages, such that said plurality of individual pipeline stages each perform a discrete multitone (DMT) symbol related operation.

23. The method of claim 22, wherein said plurality of individual pipeline stages consist of a combination of hardware and software stages.

24. The system of claim 20, wherein a nominal target clock rate frequency for said plurality of port sampling clock rates is approximately 4 kHz, and said internal clock rate is approximately 4 kHz*(N/N−

X) where N<

=69 and X>

=2.

25. A method of processing a family of digital subscriber line (xDSL) communications for a multi-port system using discrete multi-tone (DMT) symbols transmitted and received through a channel during a normal data transmission at a nominal sampling clock rate specified by an xDSL communications protocol, the method comprising the steps of:

operating a plurality of individual communications ports in the multi-port system with an operational clock rate during the normal data transmission which can exhibit some variation from the nominal sampling clock rate, such that a plurality of port operational sampling clock rates are possible during the normal data transmission;

wherein said plurality of port operational sampling clock rates can also vary from each other so as to cause each of said plurality of individual communications ports to be asynchronous with respect to other of said plurality of individual communications ports;

synchronizing said plurality of individual communication ports by using a pipeline which operates with a pipeline clock at a pipeline clock rate that is higher than the nominal clock rate and higher than any of said plurality of port operational sampling clock rates to perform signal processing operations for said plurality of individual communication ports.

26. The method of claim 25, wherein said pipeline is coupled to an analog front end circuit coder/decoder (CODEC) and said CODEC operates with a CODEC clock using a CODEC clock rate substantially higher than said pipeline clock rate.

27. The method of claim 26, wherein said pipeline clock can be disabled and or modified independently of said CODEC clock for some or all portions of said pipeline to reduce power consumption.

28. A method of processing a family of digital subscriber line (xDSL) communications involving discrete multi-tone (DMT) symbols transmitted and received through a channel during a normal data transmission at a nominal DMT symbol rate T, the method comprising the steps of:

operating each communication port from a plurality of individual communications ports using a continuous sequence of DMT symbols for communicating data; and

performing processing operations during a processing interval on said continuous sequence of DMT symbols for said plurality of individual communication ports, said pipeline having a plurality of pipeline stages that operate within said processing interval at a pipeline clock rate that is higher than the nominal DMT symbol rate; and

skipping processing operations for one or more communications ports from said plurality of individual communications ports during an idle processing interval, said idle processing interval consisting of one or more processing intervals.

29. The method of claim 28, wherein during said idle processing interval said pipeline generates a stuffing symbol, said stuffing symbol including dummy data set up in a pipeline buffer for processing by one of said plurality of pipeline stages.

30. The method of claim 29, wherein said dummy data includes an indicator bit identifying a DMT symbol as a stuffing symbol so that software and hardware task blocks making up said pipeline stages will skip any operations normally performed on such DMT symbols.

31. The method of claim 28, wherein a sufficient number of said idle processing intervals are set up by the system so that operations for all of said plurality of individual communication ports can be synchronized to said pipeline clock rate.

32. The method of claim 28, wherein said nominal DMT symbol rate is based on a nominal rate specified by an asymmetric digital subscriber line (ADSL), single pair high-speed digital subscriber line (SHDSL) and/or very high data rate digital subscriber line (VDSL) standard.