Method and structure for creating ultra low resistance damascene copper wiring

• US 6,987,059 B1
• Filed: 08/14/2003
• Issued: 01/17/2006
• Est. Priority Date: 08/14/2003
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Burke, Peter A., Sun, Sey-Shing, Lu, Hongqiang
• Primary Examiner(s): Wilson, Christian D.
• Application Number:
  US10/641,768
• Time in Patent Office: 887 Days
• Field of Search: 438/625, 438/627, 438/637, 438/642, 438/643, 438/687
• US Class Current: 438/627
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric

Abstract

A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

Claims

1. A method of forming a damascene interconnect structure in a semiconductor integrated circuit, the method comprising:

forming a trench in a first dielectric layer on a substrate;

forming a dielectric diffusion barrier film in the trench for preventing the diffusion of a copper interconnect metal layer into the first dielectric layer;

etching the dielectric diffusion barrier film anisotropically to remove the dielectric barrier film from the bottom surface of the trench to expose patterned metal;

depositing a barrier metal film in the trench to cover at least a portion of the bottom surface exposed by etching, wherein the thickness of the barrier metal film formed on the sides of the trench is approximately 20 percent or less of the thickness of the barrier metal film formed at the bottom of the trench; and

filling the trench with a copper interconnect metal layer.

2. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, further comprising a via aligned with the trench before forming a dielectric diffusion barrier film in the trench and wherein forming the dielectric diffusion barrier film in the trench is formed substantially simultaneously with the formation of the dielectric diffusion barrier film in the via.

3. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, wherein the dielectric copper diffusion barrier layer is formed by one of CVD, PECVD, MOCVD, and ALD methods.

4. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, wherein the barrier metal film further covers the sides of the trench.

5. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, wherein the wherein the thickness of the barrier metal film formed on the sides of the trench is approximately 10 percent or less of the thickness of the barrier metal film formed at the bottom of the trench.

6. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, wherein the thickness of the barrier metal film formed on the bottom of the trench lies in the range of 10 to 100 Angstroms.

7. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, wherein the thickness of the dielectric diffusion barrier film deposited lies in the range of 15 to 500 Angstroms.

8. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, wherein the thickness of the dielectric diffusion barrier film lies in the range of 50 to 100 Angstroms.

9. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, further comprising depositing a copper seed layer on the barrier metal layer prior to filling the trench with copper.

10. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 9, wherein depositing a copper adhesion promoter occurs before depositing the copper seed layer.

11. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, wherein the trench is continuously lined with at least one of the dielectric diffusion barrier film or metallic diffusion barrier layer.

12. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, wherein the dielectric diffusion barrier film includes at least one of SiC, SiN, Boron Nitride, amorphous carbon, AlN and SiOC.

13. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, wherein the dielectric diffusion barrier film is formed by surface treating the dielectric layer using high density plasma bombardment to direct Ar or H₂ particles in the dielectric layer.

14. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, wherein the anisotropic etching of the diffusion barrier film is performed by a plasma etch.

15. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 1, wherein the barrier metal deposition is controlled by a directional deposition of the barrier metal.

16. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 15, wherein the directional deposition is performed using one of ionized metal plasma (IMP), high power self-ionized plasma (SIP), physical vapor deposition (PVD), and ionized physical vapor deposition (IPVD) methods.

17. The method of forming a damascene interconnect structure in a semiconductor integrated circuit as recited in claim 15, wherein the directional deposition is performed using one of ionized metal plasma (IMP), high power self-ionized plasma (SIP), and ionized physical vapor deposition (IPVD) methods.