System with functional and selector circuits connected by mode lead

• US 6,987,382 B1
• Filed: 10/26/2000
• Issued: 01/17/2006
• Est. Priority Date: 10/31/1995
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US09/697,941
• Time in Patent Office: 1,909 Days
• Field of Search: 324/158.1, 324/73.1, 324763-766, 438 14- 18, 714/724, 714725-734
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937

Abstract

A wafer of semiconductor material is processed to form integrated circuit dies. The dies are to be singulated or separated and encapsulated for sale and use as integrated circuits. Before singulation, the dies are tested while still a part of the wafer. Die selector circuits are also formed in the wafer between the dies. The die selector circuits are used to select desired ones of the dies for testing. The die selector circuits have two or four clock signals interconnected with adjacent die selector circuits. The sequence of clock signals specifies the die or dies to be selected for testing. The interconnection of two or four clock signals facilitates testing even if the interconnection of one of more clock signals between die selector circuits is broken or opened.

Claims

1. An electronic system comprising:

A. a functional circuit having a mode input lead receiving a mode signal to place the functional circuit in one of a functional mode in which the functional circuit operates normally and a test mode in which at least part of the functional circuit is disabled; and

B. a selector circuit having a mode output lead connected to the mode input lead of the functional circuit and having a pair of clock leads separate from the functional circuit, only one of the clock leads at one time receiving a clock signal that controls the state of the mode signal formed on the mode output lead.

2. The system of claim 1 in which the test mode is a by-pass mode.

3. The system of claim 1 in which the selector circuit includes state machine circuits coupled to the pair of clock leads.

4. The system of claim 1 in which the pair of clock leads are both capable of receiving and sending clock signals.

5. The system of claim 1 in which the selector circuit includes a state machine circuit, and each of the clock leads is coupled to the state machine circuit through a clock input buffer and is connected to the other clock lead through a clock output buffer.

6. The system of claim 1 in which the selector circuit includes another pair of clock leads separate from the functional circuit and at least one of the four clock leads receives a clock signal that controls the mode signal.

7. The system of claim 1 in which the selector circuit includes another pair of clock leads separate from the functional circuit, and each of the another pair of clock leads is coupled to the state machine circuit through a clock input buffer and is connected to the other clock lead through a clock output buffer.