Iris data recovery algorithms
First Claim
Patent Images
1. In a wireless receiver, a circuit for receiving an input signal from a transmitter, the input signal including a preamble portion, a unique word portion and a data portion, the circuit comprising:
- a. a preamble detector configured to receive the input signal and to provide a preamble signal where the preamble signal is active during the preamble portion of the input signal and inactive during all portions of the input signal other than the preamble portion;
b. a DC level set circuit configured to receive the preamble signal, the input signal including the preamble portion, the unique word portion and the data portion and to receive a control signal and to provide a level set signal; and
c. a data slicer circuit coupled with the DC level set circuit to receive the level set signal and to provide an output signal;
wherein the preamble detector comprises;
i. an AC coupling for removing a direct current offset from the input signal;
ii. a first comparator for recovering a digital output from the AC coupling;
iii. a four bit delay line for detecting and for holding the preamble portion of the input signal;
iv. a lower block coupled with both the four bit delay line and the first comparator for providing the preamble signal when the four bit delay line detects the preamble portion of the input signal; and
v. a delay element for receiving the input signal and for providing a delay signal to the DC level set circuit.
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Abstract
A data recovery algorithm for implementation in a radio transmitter or receiver that includes a direct current level setting circuit with a preamble detector which will establish a threshold for a simplified decision simplified equalizer slicer that improves receiver performance in a feedback manner by utilizing an analog comparator, a one symbol long one bit resolution delay line and a summing junction.
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Citations
28 Claims
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1. In a wireless receiver, a circuit for receiving an input signal from a transmitter, the input signal including a preamble portion, a unique word portion and a data portion, the circuit comprising:
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a. a preamble detector configured to receive the input signal and to provide a preamble signal where the preamble signal is active during the preamble portion of the input signal and inactive during all portions of the input signal other than the preamble portion;
b. a DC level set circuit configured to receive the preamble signal, the input signal including the preamble portion, the unique word portion and the data portion and to receive a control signal and to provide a level set signal; and
c. a data slicer circuit coupled with the DC level set circuit to receive the level set signal and to provide an output signal;
wherein the preamble detector comprises;
i. an AC coupling for removing a direct current offset from the input signal;
ii. a first comparator for recovering a digital output from the AC coupling;
iii. a four bit delay line for detecting and for holding the preamble portion of the input signal;
iv. a lower block coupled with both the four bit delay line and the first comparator for providing the preamble signal when the four bit delay line detects the preamble portion of the input signal; and
v. a delay element for receiving the input signal and for providing a delay signal to the DC level set circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of receiving an input signal and a control signal and providing an output signal, the input signal including a preamble portion, a unique word portion and a data portion, the method comprising the steps of:
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a. receiving the input signal with a preamble detector;
b. providing a preamble signal where the preamble signal is active during the preamble portion of the input signal and inactive during all portions of the input signal other than the preamble portion;
c. receiving the preamble signal from the preamble detector, the input signal, and the control signal with a DC level set circuit;
d. providing a level set signal with the DC level set circuit;
e. receiving the level set signal from the DC level set circuit with a data slicer circuit, and f. providing the output signal with the data slicer circuit, wherein the preamble detector provides the preamble signal according to the steps of;
i. AC coupling the input signal;
ii. comparing a digital output from the AC coupling;
iii. holding the preamble portion of the input signal in a four bit delay line;
iv. providing the preamble signal when the four bit delay line detects the preamble portion of the input signal;
v. providing a delay signal to the DC level set circuit. - View Dependent Claims (15)
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16. A circuit for receiving an input signal and a control signal and providing an output signal, the input signal including a preamble portion, a unique word portion and a data portion, the circuit comprising:
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a. means for receiving the input signal with a preamble detector;
b. means for providing a preamble signal where the preamble signal is active during the preamble portion of the input signal and inactive during all portions of the input signal other than the preamble portion;
c. means for receiving the preamble signal from the preamble detector, the input signal and the control signal with a DC level set circuit;
d. means for providing a level set signal with the DC level set circuit;
e. means for receiving the level set signal from the DC level set circuit with a data slicer circuit; and
f. means for providing the output signal with the data slicer circuit; and
wherein the preamble detector comprises;
i. an AC coupling for removing a direct current offset from the input signal;
ii. a first comparator for recovering a digital output from the AC coupling;
iii. a four bit delay line for detecting and for holding the preamble portion of the input signal;
iv. a lower block coupled with both the four bit delay line and the first comparator for providing the preamble signal when the four bit delay line detects the preamble portion of the input signal; and
v. a delay element for receiving the input signal and for providing a delay signal output to the DC level set circuit. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification