Epitaxial growth for waveguide tapering

• US 6,987,912 B2
• Filed: 03/23/2004
• Issued: 01/17/2006
• Est. Priority Date: 05/31/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Morse, Michael T.
• Primary Examiner(s): Palmer, Phan T.H.
• Assistant Examiner(s): Stein, James D.
• Application Number:
  US10/808,787
• Publication Number:
  US 20040180552A1
• Time in Patent Office: 665 Days
• Field of Search: 385/129, 385/43
• US Class Current: 385/43
• CPC Class Codes: G02B 6/1228 Tapered waveguides, e.g. integrated spot-size transformers for coupling with fibres G02B6/305
• CPC Class Codes: G02B 6/131 by using epitaxial growth epitaxial growth for semiconductors H01L21/02365

Abstract

A method to form a semiconductor taper without etching the taper surfaces. In one embodiment, a semiconductor waveguide is formed on a workpiece having an unetched top surface; e.g., using a silicon insulator (SOI) wafer. A protective layer is formed on the waveguide. The protective layer is patterned and etched to form a mask that exposes a portion of the waveguide in the shape of the taper'"'"'s footprint. In one embodiment, selective silicon epitaxy is used to grow the taper on the exposed portion of the waveguide so that the taper is formed without etched surfaces. Micro-loading effects can cause the upper surface of the taper to slope toward the termination end of the taper.

Claims

1. A method for fabricating a taper, comprising:

disposing a semiconductor waveguide on a substrate;

forming a protective layer on the semiconductor waveguide;

removing a portion of the protective layer to expose a portion of the semiconductor waveguide, the exposed portion of the semiconductor waveguide defining a footprint of the taper; and

forming a semiconductor layer on the exposed portion of the semiconductor waveguide to form the taper, the taper having a termination end and a longitudinal axis, wherein the termination end has at least one unetched surface that is angled relative to the longitudinal axis.

2. The method of claim 1 wherein the semiconductor waveguide is formed using a silicon on insulator (SOI) wafer.

3. The method of claim 1 wherein the protective layer comprises an oxide.

4. The method of claim 1 wherein the semiconductor layer is formed using a selective silicon epitaxy process.

5. The method of claim 4 wherein the semiconductor layer is formed into the taper without etching the semiconductor layer.

6. The method of claim 4 wherein the semiconductor layer has a sloped upper surface.

7. The method of claim 6 wherein the sloped upper surface is formed without etching the semiconductor layer.

8. The method of claim 1 wherein forming the semiconductor layer comprises depositing semiconductor material on the protective layer and the exposed portion of the semiconductor waveguide, followed by chemical mechanical polishing to expose the protective layer.

9. The method of claim 1 wherein a insulator layer is disposed beneath the semiconductor waveguide.