Adaptive radio transceiver with polyphase calibration

• US 6,987,966 B1
• Filed: 10/18/2000
• Issued: 01/17/2006
• Est. Priority Date: 10/21/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza, Wu, Stephen, Ibrahim, Brima
• Primary Examiner(s): Milord, Marceau
• Application Number:
  US09/692,654
• Time in Patent Office: 1,917 Days
• Field of Search: 455/420, 455/423, 455/88, 455/80, 455/78, 455/76, 455/118, 455/123, 455/306, 455/307, 455/341, 455/324, 455/115.3, 455/226.1, 455/226.2, 375/347, 375/147, 375/346
• US Class Current: 455/420
• CPC Class Codes: H03B 21/01 by beating unmodulated signals of different frequencies
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 2203/45386 the AAC comprising one or more coils in the source circuit
• CPC Class Codes: H03F 2203/45526 the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 11/00 Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03H 11/126 using a single operational amplifier H03H11/1204 takes precedence; parallel-T filters H03H11/1295
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03H 11/344 : Duplexers
• CPC Class Codes: H03H 2011/0494 : Complex filters
• CPC Class Codes: H03H 21/0001 : Analogue adaptive filters
• CPC Class Codes: H03H 21/0012 : Digital adaptive filters
• CPC Class Codes: H03H 2210/025 : Capacitor
• CPC Class Codes: H03H 2210/036 : Stepwise
• CPC Class Codes: H03H 7/42 : Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 7/099 : concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 : using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04B 17/104 : of other parameters, e.g. DC offset, delay or propagation times
• CPC Class Codes: H04B 17/14 : of the whole transmission and reception path, e.g. self-test loop-back
• CPC Class Codes: H04B 17/19 : Self-testing arrangements

Abstract

An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Claims

1. A calibration circuit, comprising:

first and second digitally tunable filters; and

control logic to digitally tune the first and second filters as a function of a first parameter of a first signal output from the first filter and a second parameter of a second signal output from the second filter.

2. The calibration circuit of claim 1 wherein the first and second filters each comprises a polyphase filter.

3. The calibration circuit of claim 1 wherein the first and second filters each comprises a notch filter.

4. The calibration circuit of claim 1 further comprising a first signal strength indicator to determine the first parameter and a second signal strength indicator to determine the second parameter.

5. The calibration circuit of claim 4 wherein the first parameter comprises a first signal suppression and the second parameter comprises a second signal suppression.

6. The calibration circuit of claim 5 further comprising a comparator to compare the first signal suppression to the second signal suppression, the control logic digitally tuning the first filter if the first signal suppression is lower than the second signal suppression and digitally tuning the second filter if the second signal suppression is lower than the first signal suppression.

7. The calibration circuit of claim 6 wherein the control logic digitally tunes each of the first and second filters by providing a first digital word to the fist filter and a second digital word to the second filter.

8. The calibration circuit of claim 1 wherein the first filter comprises a first resistor and first tunable capacitor, and the second filter comprises a second resistor and a second tunable capacitor, the control logic digitally tuning the first and second capacitors.

9. The calibration circuit of claim 8 wherein the control logic digitally tunes each of the first and second capacitors by providing a first digital word to the first capacitor and a second digital word to the second capacitor.

10. The calibration circuit of claim 9 wherein the control logic tunes initially tunes the first capacitor to a first value and tunes the second capacitor to a second value different from the first value, and wherein the control logic is disabled when the first digital word equals the second digital word.

11. The calibration circuit of claim 10 wherein the first value cores a maximum value of the first capacitor and the second value comprises a minimum value of the second capacitor.

12. The calibration circuit of claim 8 wherein the first capacitor comprises a first tunable capacitor array and the second capacitor comprises a second tunable capacitor array.

13. The calibration circuit of claim 12 wherein the first and second tunable capacitor arrays each comprises a plurality of capacitors coupled in parallel, and a plurality of switches each being coupled in series to a different one of their its respective capacitors.

14. The calibration circuit of claim 13 wherein the control logic tunes the first filter with a plurality of first digital bits and tunes the second filter with a plurality of second digital bits, the first digital bits each controlling a different one of the switches in the first capacitor array and the second digital bits each controlling a different one of the switches in the second capacitor array.

15. A calibration circuit, comprising:

first and second digitally tunable filters; and

tuning means for digitally tuning the first and second filters as a function of a first parameter of a first signal output from the first filter and a second parameter of a second signal output from the second filter.

16. The calibration circuit of claim 15 wherein the first and second filters each comprises a polyphase filter.

17. The calibration circuit of claim 15 wherein the first and second filters each comprises a notch filter.

18. The calibration circuit of claim 15 wherein the first parameter comprises a first signal suppression and the second parameter comprises a second signal suppression, the tuning means further comprising means for determining the first signal strength of the first signal output from the first filter and means for determining the second signal strength of the second signal output from the second filter.

19. The calibration circuit of claim 18 wherein the tuning means further comprises means for comparing the first signal suppression with the second signal suppression, the tuning means digitally tuning the first filter if the fist signal suppression is lower than the second signal suppression and digitally tuning the second filter if the second signal suppression is lower than the first signal suppression.

20. The calibration circuit of claim 19 wherein the tuning means digitally tunes each of the first and second filters by providing a first digital word to the first filter and a second digital word to the second filter.

21. The calibration circuit of claim 15 wherein the first filter comprises a first resistor and a first tunable capacitor, and the second filter comprises a second resistor and second tunable capacitor, the tuning means digitally tuning the first and second capacitors.

22. The calibration circuit of claim 21 wherein the tuning means digitally tunes each of the first and second capacitors by providing a first digital word to the first capacitor and a second digital word to the second capacitor.

23. The calibration circuit of claim 22 wherein the tuning means comprises means for initially tuning the first capacitor to a first value and the second capacitor to a second value different from the first value, and means for latching a calibration digital word when the first digital word equals the second digital word, the calibration word being equal to the first and second digital word.

24. The calibration circuit of claim 23 wherein the first value comprises a maximum value of the first capacitor and the second value comprises a minimum value of the second capacitor.

25. The calibration circuit of claim 21 wherein the first capacitor comprises a first tunable capacitor array and the second capacitor comprises a second tunable capacitor array.

26. The calibration circuit of claim 25 wherein the first and second tunable capacitor arrays each comprises a plurality of capacitors coupled in parallel, and a plurality of switches each being coupled in series to a different one of their its respective capacitors.

27. The calibration circuit of claim 26 wherein the tuning means tunes the first filter with a plurality of first digital bits and tunes the second filter with a plurality of second digital bits, the first digital bits each controlling a different one of the switches in the first capacitor array and the second digital bits each controlling a different one of the switches in the second capacitor array.

28. A transceiver, comprising:

a calibration circuit having first and second digitally tunable filters, and control logic having a tuning output to digitally tune the first and second filters as a function of a first parameter of a first signal output from the first filter and a second parameter of a second signal output from the second filter; and

a digitally tunable transceiver filter tuned by the tuning output of the control logic.

29. The transceiver of claim 28 wherein the first and second filters each comprises a polyphase filter.

30. The transceiver of claim 28 wherein the first and second filters each comprises a notch filter.

31. The transceiver of claim 28 further comprising a first signal strength indicator to determine the first parameter and a second signal strength indicator to determine the second parameter.

32. The transceiver of claim 31 wherein the first parameter comprises a first signal suppression and the second parameter comprises a second signal suppression.

33. The transceiver of claim 32 further comprising a comparator to compare the first signal suppression to the second signal suppression, the control logic digitally tuning the first filter if the first signal suppression is lower than the second signal suppression and digitally tuning the second filter if the second signal suppression is lower than the first signal suppression.

34. The transceiver of claim 33 wherein the control logic digitally tunes each of the first and second filters by providing a first digital word to the first filter and a second digital word to the second filter.

35. The transceiver of claim 28 wherein the first filter comprises a first resistor and a first tunable capacitor, and the second filter comprises a second resistor and a second tunable capacitor, the control logic digitally tuning the first and second capacitors.

36. The transceiver of claim 35 wherein the first capacitor comprises a first tunable capacitor array and the second capacitor comprises a second tunable capacitor array.

37. The transceiver of claim 36 wherein the first and second tunable capacitor arrays each comprises a plurality of capacitors coupled in parallel, and a plurality of switches each being coupled in series to a different one of their its respective capacitors.

38. The transceiver of claim 37 wherein the control logic tunes the first filter with a plurality of first digital bits and tunes the second filter with a plurality of second digital bits, the first digital bits each controlling a different one of the switches in the first capacitor array and the second digital bits each controlling a different one of the switches in the second capacitor array.

39. The transceiver of claim 35 wherein the control logic digitally tunes each of the first and second capacitors by providing a first digital word to the first capacitor and a second digital word to the second capacitor.

40. The transceiver of claim 38 wherein the control logic tunes initially tunes the first capacitor to a first value and tunes the second capacitor to a second value different from the first value, and wherein the control logic is disabled when the first digital word equals the second digital word.

41. The transceiver of claim 40 wherein the first value comprises a maximum value of the first capacitor and the second value comprises a minimum value of the second capacitor.

42. The transceiver of claim 40 wherein the control logic tunes the transceiver component calibration digital word, the calibration digital word being equal to the first and second digital word.

43. The transceiver of claim 42 wherein the transceiver filter comprises a transceiver resistor and a tunable transceiver capacitor.

44. The transceiver of claim 43 wherein the transceiver capacitor comprises a tunable capacitor array.

45. The transceiver of claim 44 wherein the tunable capacitor array comprises a plurality of capacitors coupled in parallel and a plurality of switches each being coupled in series to a different one of the capacitors.

46. The transceiver of claim 45 wherein the calibration digital word comprises a plurality of digital bits each controlling a different one of the switches.

47. A calibration circuit, comprising:

first and second digitally tunable filters each having a tuning input;

a first signal strength indicator having an input coupled to the first filter, and an output;

a second signal strength indicator having an input coupled to the second filter, and an output;

a comparator having an input coupled to the output of the first and second signal strength indicators, and an output; and

control logic having an input coupled to the output of the comparator, and a first tuning output coupled to the tuning input of the first filter and a second tuning output coupled to the tuning input of the second filter.

48. The calibration circuit of claim 47 wherein the first and second filters each comprises a polyphase filter.

49. The calibration circuit of claim 47 wherein the first and second filters each comprises a notch filter.

50. The calibration circuit of claim 47 wherein the first filter comprises a fist resistor and a first tunable capacitor, and the second filter comprises a second resistor and a second tunable capacitor, the control logic digitally tuning the first and second capacitors.

51. The calibration circuit of claim 50 wherein the first capacitor comprises a first tunable capacitor array and the second capacitor comprises a second tunable capacitor array.

52. The calibration circuit of claim 51 wherein the first and second tunable capacitor arrays each comprises a plurality of capacitors coupled in parallel, and a plurality of switches each being coupled in series to a different one of their its respective capacitors.

53. The calibration circuit of claim 52 wherein the first tuning output comprises a plurality of first digital bits and the second tuning output comprises a plurality of second digital bits, the first digital bits each controlling a different one of the switches in the first capacitor array and the second digital bits each controlling a different one of the switches in the second capacitor array.

54. A method of calibration, comprising:

providing a reference signal to first and second digitally tunable filters; and

digitally tuning the first and second filters as a function of a first parameter of the filtered reference signal output from the first filter and a second parameter of the filtered reference signal output from the second filter.

55. The method of claim 54 wherein the first and second filters each comprises a polyphase filter.

56. The method of claim 54 wherein the first and second filters each comprises a notch filter.

57. The method of claim 54 wherein the first parameter comprises a first signal suppression and the second parameter comprises a second signal suppression.

58. The method of claim 57 further comprising comparing the first signal suppression to the second signal suppression, wherein tuning of the first and second filters comprises digitally tuning the first filter if the first signal suppression is lower than the second signal suppression and digitally tuning the second filter if the second signal suppression is lower than the first signal suppression.

59. The method of claim 58 wherein the tuning of the first and second filters further comprises providing a first digital word to the first filter and a second digital word to the second filter.

60. The method of claim 54 wherein the first filter comprises a first resistor and first tunable capacitor, and the second filter comprises a second resistor and a second tunable capacitor, the tuning of the first and second filters comprising digitally tuning the first and second capacitors.

61. The method of claim 60 wherein the first parameter comprises a first signal suppression and the second parameter comprises a second signal suppression.

62. The method of claim 61 wherein tuning of the first and second capacitors comprises initially tuning the first capacitor to a first value and the second capacitor to a second value different from the first value, the method further comprising comparing the first signal suppression to the second signal suppression with the first and second capacitors initially tuned, and wherein the tuning of the first capacitor further comprises digitally tuning the first capacitor if the first signal suppression is lower than the second signal suppression and digitally tuning the second filter if the second signal suppression is lower than the first signal suppression.

63. The method of claim 62 wherein the first value comprises a maximum value of the first capacitor and the second value comprises a minimum value of the second capacitor.

64. The method of claim 61 wherein tuning of the first and second capacitors comprises initially tuning the first capacitor to a first value and the second capacitor to a second value different from the first value, the method further comprising comparing the first signal suppression to the second signal suppression with the first and second capacitors initially tuned, and wherein the tuning of the first and second capacitors further comprises digitally tuning the first capacitor if the first signal suppression is lower than the second signal suppression.

65. The method of claim 64 wherein the tuning of the first and second capacitors further comprises providing a first digital word to the first capacitor and a second digital word to the second capacitor.

66. The method of claim 65 wherein the tuning of the first and second capacitors further comprises digitally tuning the first capacitor until the first signal suppression exceeds the second signal suppression, comparing the first digital word to the second digital word, and digitally tuning the second capacitor if the first and second digital words are not equal.

67. The method of claim 65 wherein the tuning of the first and second capacitors farther comprises digitally tuning the first capacitor until the first signal suppression exceeds the second signal suppression, comparing the first digital word to the second digital word, and latching a calibration digital word if the first and second digital words are equal, the calibration digital word being equal to the first and second digital word.

68. The method of claim 67 further comprising digitally tuning a transceiver filter with the calibration digital word.