Multiple port allocation and configurations for different port operation modes on a host

• US 6,988,161 B2
• Filed: 12/20/2001
• Issued: 01/17/2006
• Est. Priority Date: 12/20/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dammann, Ronald L., Kaniyur, Narayanan, McConnell, James A., Chan, Robert
• Primary Examiner(s): Rinehart, Mark H.
• Assistant Examiner(s): KNOLL, CLIFFORD H
• Application Number:
  US10/022,330
• Publication Number:
  US 20030120852A1
• Time in Patent Office: 1,489 Days
• Field of Search: 710/52, 710/56, 710/107, 710/316, 710/317, 710/8, 710/10, 710/11, 710/305, 709/223, 709/225, 711/147, 711/149, 714/758
• US Class Current: 710/316
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A port configuration mechanism is provided at a host for multiple port allocation and shared resource utilization to support multiple port configurations for different port operation modes on a host to handle data transfers in a switched fabric data network for scalable solutions.

Claims

1. A method of port configuration in a host comprising:

determining if a designated port supports a multi-link mode operation for data transfers, via one or more links;

if the designated port supports the multi-link mode operation, configuring and training the designated port to serve as one of a single link capable port which transfer data via a single link, a multiple link capable port which transfers data via respective multiple links, and multiple of single link ports which transfer data via a respective single link; and

generating and checking a Variant Cyclic Redundancy Code (VCRC) at the end of each data packet by computing the VCRC for most of the data packet when data is transferred with a first set of bytes, computing the VCRC for a second set of bytes that is smaller than the first set of bytes of the data packet if the data packet has some smaller subset of bytes than the first set of bytes, and computing a link CRC for link packets, selecting a CRC in accordance with a first selection signal, holding a CRC state for port designations in a plurality of CRC registers, and selecting an outout from any one of the CRC registers for CRC feedback in accordance with a second selection signal.

2. The method as claimed in claim 1, wherein the multi-link mode operation corresponds to a 4x mode operation where 4x indicates four (4) physical links between respective ports.

3. The method as claimed in claim 2, wherein the single link capable port corresponds to a 1x capable port which transfer data via a single 1x link, the multiple link capable port corresponds to a 4x capable port which transfers data via respective 4x links, and the multiple of single link ports correspond to four (4) independent 1x ports which transfer data via a respective single 1x link.

4. The method as claimed in claim 3, wherein each link is trained independently to enable the designated port to serve as the 1x capable port, the 4x capable port, or the four (4) independent 1x ports.

5. The method as claimed in claim 4, wherein the designated port is configured for the multi-link mode operation using a Portlnfo Attribute in accordance with the “

lnfiniBand™

Architecture Specification”

.

6. The method as claimed in claim 1, wherein the VCRC is generated for one packet at a time when the designated port is configured as the 1x capable port or the 4x capable port, or alternatively, for four (4) packets at a time when the designated port is configured as four (4) independent 1x ports.

7. A host node comprising:

at least one port to support data transfers, via one or more links; and

a port configuration mechanism to configure and train the port to serve as a 1x capable port which transfer data via a 1x link, a 4x capable port which transfers data via respective 4x links, or four (4) independent 1x ports which transfer data via a respective 1x link;

wherein the port configuration mechanism further includes Shared Variant Cyclic Redundancy Code (VCRC) Generation/Checking Logic to generate and to check the VCRC for every data packet, and wherein the Shared VCRC Generation/Checking Logic includes;

a 64 bit CRC Generation Block arranged to compute the VCRC for most of the data packet when data is transferred 8 bytes at a time;

a 32 bit CRC Generation Block arranged to compute the VCRC for the last 4 bytes of the data packet if the data packet has an odd number of 4 byte words, and to compute the Link CRC for link packets;

a first multiplexer arranged to select if a 64 bit or a 32 bit Generated CRC is used in accordance with a first selection signal;

a plurality of CRC Registers arranged to hold the CRC State for Port designations; and

a second multiplexer arranged to select an output from any one of the CRC Registers for CRC feedback, via a CRC feedback bus in accordance with a second selection signal.

8. The host node as claimed in claim 7, wherein the port is configured for a multi-link mode operation using a Portlnfo Attribute in accordance with the “

InfiniBand™

Architecture Specification”

.

9. The host node as claimed in claim 7, wherein the VCRC is generated for one data packet at a time when the port is configured as one 1x capable port or as one 4x capable port.

10. The host node as claimed in claim 9, wherein the VCRC is generated for four (4) data packets at a time when the port is configured as four (4) independent 1x capable ports.

11. The host node as claimed in claim 7, wherein the port configuration mechanism further comprises four independent Link Training Logic Blocks arranged to train each link independently to enable the port to serve as the 1x capable port, the 4x capable port, or the four (4) independent 1x ports.

12. The host node as claimed in claim 11, wherein, when the port is configured as one 1x capable port or one 4x capable port, only one Link Training Logic Block is enabled and the remainder Logic Blocks are disabled.

13. The host node as claimed in claim 11, wherein, when the port is configured as four (4) independent 1x capable ports, all four Link Training Logic Blocks are enabled and each 1x capable port operates independently from each other.

14. A computer readable medium comprising instructions that, when executed by a host node in a switched fabric including end nodes and switches interconnected via one or more links, cause the host node to support multiple port configurations on the host node by:

determining if a designated port in the host node supports a multi-link mode operation for data transfers, via one or more links;

if the designated port supports the multi-link mode operation, configuring and training the designated port to serve as one of a single link capable port which transfer data via a single link, a multiple link capable port which transfers data via respective multiple links, and multiple of single link ports which transfer data via a respective single link; and

generating and checking a Variant Cyclic Redundancy Code (VCRC) at the end of each data packet by computing the VCRC for most of the data packet when data is transferred with a first set of bytes, computing the VCRC for a second set of bytes that is smaller than the first set of bytes of the data packet if the data packet has a smaller subset of bytes than the first set of bytes, and computing a link CRC for link packets, selecting a CRC in accordance with a first selection signal, holding a CRC state for port designations in a plurality of CRC registers, and selecting an output from any one of the CRC registers for CRC feedback in accordance with a second selection signal.

15. The computer readable medium as claimed in claim 14, wherein the single link capable port corresponds to a 1x capable port which transfer data via a single 1x link, the multiple link capable port corresponds to a 4x capable port which transfers data via respective 4x links, and the multiple of single link ports correspond to four (4) independent 1x ports which transfer data via a respective single 1x link.

16. The computer readable medium as claimed in claim 14, wherein each link is trained independently to enable the designated port to serve as the 1x capable port, the 4x capable port, or the four (4) independent 1x ports.

17. The computer readable medium as claimed in claim 14, wherein the designated port is configured for the multi-link mode operation using a Portlnfo Attribute in accordance with the “

lnfiniBand™

Architecture Specification”

.

18. A host node comprising:

at least one port to support a multi-link mode operation for data transfers, via one or more links; and

a port configuration mechanism to configure and train the at least one port to serve as one of a single link capable port which transfer data via a single link, a multiple link capable port which transfers data via respective multiple links, and multiple single link ports which transfer data via a respective single link;

wherein the port configuration mechanism further includes Shared Variant Cyclic Redundancy Code (VCRC) Generation/Checking Logic to generate and to check the VCRC for every data packet, and wherein the Shared VCRC Generation/Checking Logic includes;

a first CRC generator arranged to compute a first VCRC for most of the data packet when data is transferred in a first size;

a second CRC generator arranged to compute a second VCRC for a portion of the data packet if the data packet has a second size, and to compute the Link CRC for link packets;

a first multiplexer arranged to select if the first or the second computed VCRC is used in accordance with a first selection signal;

a plurality of CRC registers arranged to hold a CRC State for port designations; and

a second multiplexer arranged to select an output from any one of the CRC registers for CRC feedback in accordance with a second selection signal.

19. The host node as claimed in claim 18, wherein the port is configured for a multi-link mode operation using a Portlnfo Attribute in accordance with the “

lnfiniBand™

Architecture Specification”

.

20. The host node as claimed in claim 18, wherein the VCRC is generated for one data packet at a time when the port is configured as one 1x capable port or as one 4x capable port.

21. The host node as claimed in claim 20, wherein the VCRC is generated for four (4) data packets at a time when the port is configured as four (4) independent 1x capable ports.

22. The host node as claimed in claim 18, wherein the port configuration mechanism further comprises four independent Link Training Logic Blocks arranged to train each link independently to enable the port to serve as the 1x capable port, the 4x capable port, or the four (4) independent 1x ports.

23. The host node as claimed in claim 22, wherein, when the port is configured as one 1x capable port or one 4x capable port, only one Link Training Logic Block is enabled and the remainder Logic Blocks are disabled.

24. The host node as claimed in claim 22, wherein, when the port is configured as four (4) independent 1x capable ports, all four Link Training Logic Blocks are enabled and each 1x capable port operates independently from each other.