Scalable architecture based on single-chip multiprocessing

• US 6,988,170 B2
• Filed: 10/24/2003
• Issued: 01/17/2006
• Est. Priority Date: 06/10/2000
• Status: Expired due to Term

• Current Assignee: SK Hynix Inc.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Barroso, Luiz Andre, Nowatzyk, Andreas, Gharachorloo, Kourosh
• Primary Examiner(s): Elmore, Stephen C.
• Assistant Examiner(s): Li, Zhuo H.
• Application Number:
  US10/693,388
• Publication Number:
  US 20040088487A1
• Time in Patent Office: 816 Days
• Field of Search: 711141-148, 711122-123, 711/127, 711117-119, 711/5, 711/120, 711/130, 711/150, 711/157, 711/203.5, 365/230.03, 365/230.05, 365/230.04, 709/213, 709/216, 370/351, 370/356, 370/395.5
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0826 Limited pointers directories; State-only directories without pointers
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads. A showcase example of the chip-multiprocessing system, called the PIRAHNA™ system, is a highly integrated processing node with eight simpler ALPHA™ processor cores. A method for scalable chip-multiprocessing is also provided.

Claims

1. A chip-multiprocessing system with scalable architecture, comprising on a single chip:

a plurality of processor cores;

a two-level cache hierarchy including a pair of instruction and data caches for, and private to, each processor core, the pair being first level caches;

a second level cache with a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores, the second level cache being modular with a plurality of interleaved modules;

one or more memory controllers capable of operatively communicating with the two-level cache hierarchy and with an off-chip memory;

a cache coherence protocol;

one or more coherence protocol engines;

an intra-chip switch; and

an interconnect subsystem.

2. A chip-multiprocessing system as in claim 1, wherein the scalable architecture is targeted at parallel commercial workloads.

3. A chip-multiprocessing system as in claim 1, further comprising on a single I/O chip (input output chip):

a processor core similar in structure and function to the plurality of processor cores;

a single-module second-level cache with controller;

an I/O router; and

a memory that participates in the cache coherence protocol.

4. A chip-multiprocessing system as in claim 1, wherein the plurality of core processors are each a single-issue, in-order processor configured with a pipelined datapath and hardware support for floating-point operations.

5. A chip-multiprocessing system as in claim 1, wherein the plurality of processor cores are each capable of executing an instructions set of the ALPHA™

processing core.

6. A chip-multiprocessing system as in claim 1, wherein the plurality of processor cores are each configured with a branch target buffer, pre-compute logic for branch conditions, and a fully bypassed datapath.

7. A chip-multiprocessing system as in claim 1, wherein each of the plurality of processor cores is capable of separately interfacing with either of the instruction and data caches, and wherein each of the caches is configured for single-cycle latency.

8. A chip-multiprocessing system as in claim 1, wherein the interconnect subsystem includes a network router, a packet switch and input and output queues.

9. A chip-multiprocessing system as in claim 1, wherein the single chip creates a node, and wherein the coherence protocol engines include a home engine and a remote engine which support shared memory across multiple nodes.

10. A chip-multiprocessing system as in claim 1, further comprising:

a system control module that takes care of system initialization and maintenance including configuration, interrupt handling, and performance monitoring.

11. A chip-multiprocessing system as in claim 1, wherein the second level cache is interleaved into eight modules.

12. A chip-multiprocessing system as in claim 1, wherein each of the instruction and data caches is a two-way set-associative, blocking cache with virtual indices and physical tags.

13. A chip-multiprocessing system as in claim 1, wherein each instruction cache is kept coherent by hardware.

14. A chip-multiprocessing system as in claim 1, wherein each of the second level cache modules includes an N-way set associative cache and uses a round-robin or least-recently-loaded replacement policy if an invalid block is not available.

15. A chip-multiprocessing system as in claim 1, wherein the pair of instruction and data caches includes a first state field per each cache line present therein the first state field having bits related to the MESI (modified, exclusive, shared, invalid) protocol.

16. A chip-multiprocessing system as in claim 15, wherein the second level cache maintains a duplicate of the first state fields from the first-level pairs of instruction and data caches, the duplicate being maintained in order to avoid the need for a first-level cache lookup for cache lines that map to given addresses of corresponding requested cache lines.

17. A chip-multiprocessing system as in claim 15, wherein the second level cache holds a second state field for each cache line present therein, the second state field having bits related to the MESI protocol, wherein the second level cache maintains a duplicate of the first state fields, and wherein on every second level cache access the duplicate first state fields and the second state fields are accessed in parallel.

18. A chip-multiprocessing system as in claim 1, wherein the single chip creates a node, and wherein information about sharing of data across nodes is kept in a directory in a memory accessed via the memory controllers.

19. A chip-multiprocessing system as in claim 18, wherein the second level cache includes a controller, and wherein manipulation and interpretation of the directory is done by the protocol engines, although the controller also interprets the directory, but merely for determining whether a cache line is cached remotely to the single chip.

20. A chip-multiprocessing system as in claim 1, wherein the interconnect subsystem includes at least one datapath, and wherein the interconnect subsystem is a crossbar configured with a uni-directional, push-only interface, and is capable of scheduling data transfers according to datapaths availability, pre-allocating datapaths, speculatively asserting a requester'"'"'s grant signal, and supporting back-to-back transfers without dead-cycles between transfers.

21. A chip-multiprocessing system as in claim 1, wherein the memory controller includes a memory access controller with high speed interface circuitry and a memory controller engine capable of scheduling second-level cache memory access.

22. A chip-multiprocessing system as in claim 1, wherein the coherence protocol engines are implemented as similarly structured microprogrammable controllers, although each of them has its respective microcode.

23. A chip-multiprocessing system as in claim 1, wherein each of the coherence protocol engines is configured with an input stage, a microcode-controlled execution stage and an output stage.

24. A chip-multiprocessing system as in claim 1, wherein at least one of the coherence protocol engines is configured to execute protocol code that includes instructions named Send, Receive, Lsend, Lreceive, Test, Set and Move.

25. A method for scalable chip-multiprocessing, comprising:

(a) providing on a single chip

(i) a plurality of processor cores,

(ii) a two-level cache hierarchy including

(A) a pair of instruction and data caches for, and private to, each processor core, the pair being first level caches, and

(B) a second level cache with a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores, the second level cache being modular with a plurality of interleaved modules,

(iii) one or more memory controllers capable of operatively communicating with the two-level cache hierarchy and with an off-chip memory,

(iv) a cache coherence protocol,

(v) one or more coherence protocol engines,

(vi) an intra-chip switch, and

(vii) an interconnect subsystem,

(b) wherein the single chip creates a node; and

(c) providing one or more than one of the nodes to create, in a modular scalable fashion, a glueless multiprocessor.

26. A method for scalable chip-multiprocessing as in claim 25, further comprising:

providing on a single I/O chip (input output chip)

a processor core similar in structure and function to the plurality of processor cores,

a single-module second-level cache with controller,

an I/O router, and

a memory that participates in the cache coherence protocol.

27. A single-chip multiprocessing system, comprising:

a plurality of processor cores;

a two-level cache hierarchy including a pair of instruction and data caches for, and private to, each processor core, the pair being first level caches;

a second level cache with a relaxed inclusion property that is logically shared by the plurality of processor cores, the second level cache being modular with a plurality of interleaved modules; and

a plurality of memory controllers, each of the plurality of memory controllers being associated with one of the plurality of interleaved modules, each of the plurality of the memory controllers being adapted to communicate with the two-level cache hierarchy and with an off-chip memory.

28. The single-chip multiprocessing system set forth in claim 27, wherein each of the plurality of interleaved modules of the second level cache comprises dedicated tag and data storage.

29. A chip-multiprocessing system, comprising:

a plurality of processor cores;

a two-level cache hierarchy including a pair of instruction and data caches for, and private to, each processor core, the pair being first level caches;

a second level cache with a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores, the second level cache being modular with a plurality of interleaved modules, wherein each of the plurality of interleaved modules of the second level cache has its own controller, on chip tag and data storage, and wherein each module being attached to one of the memory controllers which interfaces to a bank of memory chips, and each bank of memory chips includes DRAM (dynamic random access memory) chips;

one or more memory controllers capable of operatively communicating with the two-level cache hierarchy and with an off-chip memory;

a cache coherence protocol;

one or more coherence protocol engines;

an intra-chip switch; and

an interconnect subsystem.