Method and apparatus for compiling source code to configure hardware

• US 6,988,192 B2
• Filed: 02/11/2002
• Issued: 01/17/2006
• Est. Priority Date: 02/11/2002
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Snider, Gregory S.
• Primary Examiner(s): Cao, Chun
• Application Number:
  US10/068,886
• Publication Number:
  US 20030154466A1
• Time in Patent Office: 1,436 Days
• Field of Search: None
• US Class Current: 713/1
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

An embodiment of the invention includes, parsing a source code, performing a plurality of optimizations on the parsed code, generating a plurality of configuration instruction sets based on the optimized source code and automatically selecting one of the plurality of generated configuration instruction sets according to a user defined criteria, the selected configuration instruction set being used to configure hardware.

Claims

1. A method of compiling, the method comprising the steps of:

parsing a source code;

performing a plurality of optimizations on the parsed code;

generating a plurality of configuration instruction sets based on the optimized source code; and

automatically selecting one of the plurality of generated configuration instruction sets by comparing characteristics of the configuration instruction sets to a user-defined criteria, the selected configuration instruction set being used to configure hardware.

2. The method according to claim 1, wherein the step of parsing further comprises the step of:

parsing the source code into portions, wherein the portions include computations.

3. The method of claim 1, wherein the step of automatically selecting further comprises the steps of:

determining characteristics for the each of the plurality of the configurable instruction sets; and

selecting one of the plurality of configuration instructions sets based on determined the characteristics of that set, wherein the characteristics are compared to the user-defined criteria.

4. The method according to claim 3, wherein the step of determining characteristics comprises receiving simulation results associated with each configuration instruction set.

5. The method according to claim 1, wherein the step of performing optimizations further comprises the steps of:

determining whether operations parsed from the source code are on a critical path;

determining whether operations parsed from the source code have a predetermined amount of slack; and

determining whether operations parsed from the source code are operable to share resources.

6. The method according to claim 5, wherein the critical path is a plurality of operations being performed simultaneously.

7. The method according to claim 1, wherein the user defined criteria is the speed to complete a computation, size of circuit, and circuit power.

8. The method according to claim 1, further comprising the step of:

generating an internal representation of the source code.

9. The method according to claim 1, further comprising the step of:

configuring hardware using the selected configuration instruction set.

10. The method according to claim 9, wherein the hardware includes one of:

an FPGA or a custom integrated circuit.

11. A method for compiling source code comprising steps of:

generating an internal representation of the source code;

analyzing data flow properties of the internal representation in order to optimize the internal representation;

automatically generating a plurality of configuration instruction sets based on the optimized internal representation;

generating a plurality of configuration instruction sets based on the optimized source code; and

automatically selecting one of the plurality of generated configuration instruction sets by comparing characteristics of the configuration instruction sets to a user defined criteria, the selected configuration instruction set being used to configure hardware.

12. The method according to claim 11, wherein analyzing the data flow properties further comprises the steps of:

determining whether operations parsed from the source code are on a critical path;

determining whether operations parsed from the source code have a predetermined amount of slack; and

determining whether operations parsed from the source code are operable to share resources.

13. The method according to claim 12, wherein the critical path is a plurality of computations being performed simultaneously.

14. The method according to claim 11, wherein the step of automatically selecting further comprises the steps of:

determining characteristics for the each of the plurality of the configurable instruction sets; and

selecting one of the plurality of configuration instructions sets based on determined the characteristics of that set, wherein the characteristics are compared to the user-defined criteria.

15. The method according to claim 14, wherein the user defined criteria is the speed to complete a computation, size of circuit, and circuit power.

16. The method according to claim 11, further comprising the step of:

configuring hardware using the selected configuration instruction set.

17. A system for using software to generate a circuit comprising:

a processor operable to receive source code;

a complier automatically generating a plurality of configuration sets from the received source code and selecting one of the plurality of configuration sets by comparing characteristics of the configuration instruction sets to user defined criteria;

and a configurable hardware device receiving the selected configuration instruction set and being configured based on the received configuration instruction set.

18. The system of claim 17, wherein the configurable hardware device is a FPGA or custom circuit.

19. The system according to 17, wherein the compiler parses the source code into an internal representation.

20. The system according to claim 17, wherein the compiler analyzes an internal representation of the source code to generate the plurality of configuration instruction sets.

21. The system according to claim 20, wherein the data flow system determines whether operations parsed from the source code are on a critical path;

determines whether operations parsed from the source code have a predetermined amount of slack; and

determines whether operations parsed from the source code are operable to share resources.

22. The system of claim 17, wherein the system further comprises:

a memory device connected to the processor and stores the plurality of configuration instruction sets.

23. An apparatus for compiling, the apparatus comprising:

means for parsing a source code;

means for performing a plurality of optimizations on the parsed code;

means for generating a plurality of configuration instruction sets based on the optimized source code; and

means for automatically selecting one of the plurality of generated configuration instruction sets by comparing characteristics of the configuration instruction sets to a user-defined criteria, the selected configuration instruction set being used to configure hardware.

24. The apparatus according to claim 23, wherein the means for parsing further comprises:

means for parsing the source code into portions, wherein the portions include computations.

25. The apparatus of claim 23, wherein the means for automatically selecting further comprises:

means for determining characteristics for the each of the plurality of the configurable instruction sets; and

means for selecting one of the plurality of configuration instructions sets based on determined the characteristics of that set, wherein the characteristics are compared to the user-defined criteria.

26. The method according to claim 25, wherein the means for determining characteristics comprises receiving simulation results associated with each configuration instruction set.