Method of making an integrated inductor

• US 6,988,307 B2
• Filed: 08/29/2002
• Issued: 01/24/2006
• Est. Priority Date: 11/23/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gardner, Donald S.
• Primary Examiner(s): Kim, Paul D
• Application Number:
  US10/230,734
• Publication Number:
  US 20030005572A1
• Time in Patent Office: 1,244 Days
• Field of Search: 296/021, 2960313-60316, 296/031.8, 296/06, 296/09, 336/65, 336/83, 336/200, 336206-208, 336/223, 336/232, 336/233, 257/531, 427/127, 427/128, 216/22, 216/39, 216/41, 216/48
• US Class Current: 29/602.1
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0046 with a conductive path having a bridge
• CPC Class Codes: H01F 2017/008 Electric or magnetic shielding of printed inductances
• CPC Class Codes: H01F 41/042 by thin film techniques
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49032 Fabricating head structure or component thereof
• CPC Class Codes: Y10T 29/49043 Depositing magnetic layer or coating
• CPC Class Codes: Y10T 29/49044 Plural magnetic deposition layers
• CPC Class Codes: Y10T 29/49048 Machining magnetic material [e.g., grinding, etching, polishing]
• CPC Class Codes: Y10T 29/49052 by etching
• CPC Class Codes: Y10T 29/49073 by assembling coil and core
• CPC Class Codes: Y10T 29/49075 : including permanent magnet or core
• CPC Class Codes: Y10T 29/49078 : Laminated
• CPC Class Codes: Y10T 29/49156 : with selective destruction of conductive paths

Abstract

An inductor comprises a substrate comprising a semiconductor material, a first dielectric layer over the substrate, a magnetic layer over the first dielectric layer, a second dielectric layer over the magnetic layer, and a conductor over the second dielectric layer.

Claims

1. A method comprising:

forming a first dielectric layer over a substrate comprising a semiconductor material;

forming a magnetic layer over the first dielectric layer;

forming a second dielectric layer over the magnetic layer;

forming a conductor over the second dielectric layer; and

patterning the first dielectric layer and the magnetic layer to define one or more trenches such that the conductor defines a signal path along the one or more trenches.

2. The method of claim 1, wherein the forming the magnetic layer comprises forming the magnetic layer comprising cobalt.

3. The method of claim 1, wherein the forming the magnetic layer comprises forming the magnetic layer comprising an amorphous alloy comprising cobalt.

4. The method of claim 1, wherein the forming the magnetic layer comprises forming the magnetic layer comprising an amorphous alloy comprising cobalt and zirconium.

5. The method of claim 1, wherein the forming the magnetic layer comprises forming the magnetic layer comprising an amorphous alloy comprising cobalt;

zirconium; and

tantalum, niobium, or rhenium.

6. The method of claim 1, comprising patterning the magnetic layer to define at least one slot.

7. The method of claim 1, comprising:

forming a third dielectric layer over the conductor; and

forming another magnetic layer over the third dielectric layer.

8. The method of claim 7, comprising patterning the other magnetic layer to define at least one slot.

9. The method of claim 7, comprising connecting the magnetic layers.

10. The method of claim 1, comprising patterning the conductor to define a spiral-shaped signal path having at least one turn.