Method of fabrication of stacked semiconductor devices

• US 6,989,285 B2
• Filed: 08/03/2004
• Issued: 01/24/2006
• Est. Priority Date: 05/20/1996
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ball, Michael B.
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US10/911,862
• Publication Number:
  US 20050009236A1
• Time in Patent Office: 539 Days
• Field of Search: 438/33, 438/57, 438/68, 438/106, 438/107, 438/109, 438/110, 438/113, 438/114, 438/118, 438/119, 438/455, 438/458, 438/459, 438/460, 438/462, 438/464, 257/678, 257/685, 257/686, 257/723, 257/724, 257/734, 257/777, 257/782, 257/783
• US Class Current: 438/33
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method for increasing integrated circuit density is disclosed comprising stacking an upper wafer and a lower wafer, each of which having fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complementary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be diced into individual die pairs or wafer portions containing more than one die pair.

Claims

1. A method of stacking semiconductor wafer segments, each of the semiconductor wafer segments including integrated circuitry, comprising:

providing a first semiconductor substrate segment having a first side including integrated circuitry thereon and having a back side;

providing at least one second semiconductor substrate segment having a first side including a plurality of integrated circuits thereon, having a back side, and having a notch through the at least one second semiconductor substrate segment, the notch extending between and substantially perpendicular to a circuitry side and a back side of the at least one second semiconductor substrate segment;

stacking the first semiconductor substrate segment and the at least one second semiconductor substrate segment in at least partially superimposed relationship to form a multi-level stack of semiconductor substrate segments having portions thereof attached to each other;

separating the multi-level stack of semiconductor substrate segments to form at least two semiconductor substrate segment stacks, each multi-level stack of the at least two semiconductor substrate segment stacks comprising a first semiconductor substrate segment having a side including integrated circuitry and a back side and at least one second semiconductor substrate segment having a side including integrated circuitry and a back side; and

stacking the at least two semiconductor substrate segments in at least partially superimposed relationship having bond pads on the first semiconductor substrate segment of at least one of the at least two semiconductor substrate segment stacks on a side adjacent the at least one second semiconductor substrate segment of the multi-level semiconductor substrate segment stack at a periphery thereof.

2. The method of claim 1, further including:

stacking the semiconductor substrate segments of the at least one semiconductor substrate segment stack with the integrated circuitry side of the first semiconductor substrate segment proximate the back side of the at least one second semiconductor substrate segment; and

locating the bond pads on the integrated circuitry side of the first semiconductor substrate segment.

3. The method of claim 1, further including:

adhesively attaching the first and the at least one second semiconductor substrate segments of the at least one semiconductor substrate segment stack.

4. The method of claim 1, further including

disposing a heat sink element between the first and the at least one second semiconductor substrate segments.

5. The method of claim 1, further comprising:

connecting at least one of the first and the at least one second semiconductor substrate segments to conductors of a substrate.

6. The method of claim 5, wherein the connection comprises a connection element selected from a group comprising bond wires and traces of flex circuits.

7. A method of stacking semiconductor wafers, each of the semiconductor wafers including integrated circuitry, comprising:

providing a first semiconductor wafer having a first side including integrated circuitry and having a back side;

providing at least one other semiconductor wafer having a first side including integrated circuitry, having a back side, and having a notch; and

stacking the first semiconductor wafer and the at least one other semiconductor wafer having at least portions thereof attached, bond pads on the first semiconductor wafer of the stack on a side adjacent the at least one other semiconductor wafer at a periphery thereof.

8. The method of claim 7, further including:

stacking the first semiconductor wafer and the at least one other semiconductor wafer with a third semiconductor wafer, having the integrated circuitry side of the first semiconductor wafer segment proximate a back side of the third semiconductor wafer.

9. The method of claim 7, wherein adhesively attaching the first semiconductor wafer and the at least one other semiconductor wafer comprises:

adhesively attaching the first semiconductor wafer and the at least one other semiconductor wafer with a dielectric adhesive.

10. The method of claim 7, further including:

disposing a heat sink element between the first semiconductor wafer and the at least one other semiconductor wafer.

11. The method of claim 7, further comprising:

connecting at least one of the first semiconductor wafer and the at least one other semiconductor wafer to conductors of a substrate.

12. The method of claim 11, wherein a direct electrical connection is achieved with a connection element selected from a group comprising bond wires and traces of flex circuits.

13. The method of claim 7, wherein the first semiconductor wafer and the at least one other semiconductor wafer are stacked with the integrated circuit side of the first semiconductor wafer facing the back side of the at least one other semiconductor wafer, and wherein the bond pads are located on the integrated circuit side of the first semiconductor wafer.

14. A method of stacking at least two wafer segments, a first wafer segment having at least some integrated circuitry on a first side thereof and having a back side, a second wafer segment having a first side having at least one integrated circuit thereon and having a back side, the method comprising:

stacking the first wafer segment and the second wafer segment in at least partially superimposed relationship to form a stack of wafer segments having portions thereof attached, each stack of wafer segments comprising a first wafer segment having a first side including integrated circuitry and a back side and a second wafer segment having a side including integrated circuitry and a back side;

stacking another first wafer segment and the second wafer segment to form a stack of wafer segments, each stack of wafer segments comprising a first wafer segment having a first side including integrated circuitry and a back;

stacking the at least two wafer segment stacks forming a multi-level stack having bond pads on the first wafer segment of the multi-level stack on a side adjacent the at least one second wafer segment of the multi-level stack at a periphery thereof; and

forming a notch through the second wafer segment of the multi-level stack, the notch extending between and substantially perpendicular to a circuitry side and a back side of the at least one second wafer segment to provide access to at least one peripheral bond pad of the first wafer segment of the multi-level stack.

15. The method of claim 14, further including:

stacking the wafer segments forming the multi-level stack with the integrated circuitry side of the first wafer segment proximate the back side of the second wafer segment; and

locating the bond pads on the integrated circuitry side of the first wafer segment.

16. The method of claim 14, further including:

adhesively attaching the first wafer segment and the second wafer segments of the multi-level stack.

17. The method of claim 14, further including

disposing a heat sink element between the first wafer segments and the second wafer segments.

18. The method of claim 14, further comprising:

connecting at least one of the first wafer segments and the second wafer segments to conductors of a substrate.

19. The method of claim 18, wherein the connection comprises a connection element selected from a group comprising bond wires and traces of flex circuits.