Conformal barrier liner in an integrated circuit interconnect

• US 6,989,604 B1
• Filed: 09/26/2003
• Issued: 01/24/2006
• Est. Priority Date: 06/06/2002
• Status: Active Grant

• Current Assignee: Innovative Foundry Technologies LLC
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sanchez, Jr., John E., Ngo, Minh Van, Woo, Christy Mei-Chu, Avanzino, Steven C.
• Primary Examiner(s): Andujar, Leonardo
• Application Number:
  US10/672,103
• Time in Patent Office: 851 Days
• Field of Search: 257750-776
• US Class Current: 257/774
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers

Abstract

An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

Claims

1. An integrated circuit comprising;

a substrate having a semiconductor device thereon;

a first stop layer over the substrate having a portion open to the semiconductor device;

a first dielectric layer over the first stop layer having an opening provided therein having sidewalls in the first dielectric layer;

a first conformal barrier liner in the opening, the first conformal barrier liner having only vertical portions of a constant thickness on the sidewalls of the opening in the first dielectric layer, the vertical portions of the first conformal barrier liner on the sidewalls acting as a barrier to diffusion of conductor core material to the first dielectric layer;

a treated area on the first conformal barrier liner and the first stop layer to increase adhesion properties thereof;

a second stop layer over the first dielectric layer and having a stepped opening provided therein; and

a first conductor core in the opening over the vertical portions of the first conformal barrier liner and the first stop layer, the first conductor core connected to the semiconductor device.

2. The integrated circuit as claimed in claim 1 including:

a second dielectric layer over the second stop layer and having an opening provided therein having sidewalls;

a third stop layer over the second dielectric layer and having an opening provided therein;

a second conformal barrier liner in the opening in the second dielectric layer, the second conformal barrier liner having only vertical portions of a second constant thickness on the sidewalls of the openings in the second dielectric layer and the second dielectric layer;

a treated area on the second conformal barrier liner and the second stop layer for increasing adhesion properties thereof; and

the first conductor core in the opening over the vertical portions of the second conformal barrier liner and the second stop layer, the second conductor core connected to the first conductor core through the opening in the via stop layer.

3. The integrated circuit as claimed in claim 1 wherein the first stop layer over the substrate has a thickness “

t” and

the second stop layer has a thickness “

T”

of greater than about 2t.

4. The integrated circuit as claimed in claim 1 wherein the first conformal barrier liner has a region selected from a group consisting of silicon-enriched, wetting layer covered, and a combination thereof.

5. The integrated circuit as claimed in claim 1 wherein the first conformal barrier liner is a nonconductive barrier material selected from a group consisting of a nitride, a BLok, a carbide, an oxynitride, and a combination thereof.

6. The integrated circuit as claimed in claim 1 wherein the first conductor core is a material selected from a group consisting of copper, aluminum, gold, silver, compounds thereof, and combinations thereof.

7. The integrated circuit as claimed in claim 1 wherein the first dielectric layer comprises a low dielectric constant material.

8. An integrated circuit comprising;

a substrate having a semiconductor device thereon;

a device dielectric layer over the substrate;

a first channel stop layer over the substrate and the device dielectric layer having a portion open to the semiconductor device;

a first channel dielectric layer over the first channel stop layer having a first channel opening provided therein having sidewalls in the first channel dielectric layer;

a first conformal-barrier liner in the opening, the first conformal barrier liner having only vertical portions on the sidewalls of the opening in the first channel dielectric layer, the vertical portions of the first conformal barrier liner on the sidewalls acting as a barrier to diffusion of conductor core material to the first channel dielectric layer;

a treated area on the first conformal barrier liner and the first channel stop layer to increase adhesion properties thereof;

a via stop layer under the first channel dielectric layer and having a stepped opening provided therein; and

a first conductor core in the opening over the vertical portions of the first conformal barrier liner and the first channel stop layer, the first conductor core connected to the semiconductor device.

9. The integrated circuit as claimed in claim 8 including:

a via dielectric layer under the first channel stop layer and having a via opening provided therein having sidewalls;

the first channel stop layer having a stepped opening provided therein, a first portion of the stepped opening of the same size as the opening in the first channel dielectric layer and a second portion of the stepped opening of the same size as the opening in the via stop layer;

a second conformal barrier liner in the via opening, the second conformal barrier liner having only vertical portions on the sidewalls of the via opening, the vertical portion of the second conformal barrier liner on the sidewalls of the via opening acting as a barrier to diffusion of first conductor core material to the via dielectric layer;

a treated area on the second conformal barrier liner and the via stop layer to increase adhesion properties thereof; and

the first conductor core in the via opening over the vertical portions of the second conformal barrier liner and the first channel stop layer.

10. The integrated circuit as claimed in claim 8 wherein the via stop layer has a thickness “

t” and

the first channel stop layer has a thickness “

T”

of greater than about twice the thickness “

t”

distal from the stepped opening.

11. The integrated circuit as claimed in claim 8 wherein the first and second conformal barrier liners have regions selected from a group consisting of silicon-enriched, wetting layer covered, and a combination thereof.

12. The integrated circuit as claimed in claim 8 wherein the first conformal barrier liner comprises a nonconductive barrier material selected from a group consisting of a nitride, a BLok, a carbide, an oxynitride, and a combination thereof in a thickness between 20 Å

and 70 Å

.

13. The integrated circuit as claimed in claim 8 wherein the first channel dielectric layer comprises a porous low dielectric constant material having a dielectric constant under 3.9.

14. The integrated circuit as claimed in claim 8 wherein the first conductor core comprises a material selected from a group consisting of copper, aluminum, gold, silver, compounds thereof, and combinations thereof.