Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers

• US 6,989,607 B2
• Filed: 07/29/2003
• Issued: 01/24/2006
• Est. Priority Date: 03/20/2002
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Darbha, Krishna, Jimarez, Miguel A., Sathe, Sanjeev B., Woychik, Charles G., Reiss, Matthew M.
• Primary Examiner(s): Pham, Hoai
• Assistant Examiner(s): NGUYEN, DILINH P
• Application Number:
  US10/629,469
• Publication Number:
  US 20040021205A1
• Time in Patent Office: 910 Days
• Field of Search: 257/685, 257/686, 257/723, 257/747, 257/618, 257/620, 257/778, 257737-738, 438/110, 438/113, 438/458, 438/464
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Abstract

A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.

Claims

1. An electronic structure, comprising:

a substrate, wherein the substrate is selected from the group consisting of a ceramic chip carrier, an organic chip carrier, and a printed circuit board; and

a semiconductor device electrically coupled to the substrate, wherein the semiconductor device is divided into a plurality of segments, wherein at least one segment of the plurality of segments is not congruent with respect to a remaining segment of the plurality segments, wherein the substrate comprises a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the semiconductor device, and wherein said at least one segment of the plurality of segments is a circular segment.

2. The electronic structure of claim 1, wherein the length of each segment of the semiconductor device is greater than or equal to 5 millimeters.

3. The electronic structure of claim 1, wherein a first segment and a second segment of the plurality of segments are congruent with respect to each other.

4. The electronic structure of claim 1, wherein at least one segment of the plurality of segments is a square segment.

5. The electronic structure of claim 1, wherein the substrate is symmetrically coupled to each segment of the semiconductor device.

6. The electronic structure of claim 1, wherein the semiconductor device is a semiconductor chip.

7. A method for forming an electronic structure, comprising:

dividing a semiconductor device into a plurality of segments, and

electrically coupling a substrate to each segment of the plurality of segments of the semiconductor device, wherein the substrate is selected from the group consisting of a ceramic chip carrier, an organic chip carrier, and a printed circuit board, wherein at least one segment of the plurality of segments is not congruent with respect to a remaining segment of the plurality of segments, and wherein the substrate comprises a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the semiconductor device, and wherein said at least one segment of the plurality of segments is a circular segment.

8. The method of claim 7, wherein each segment of the semiconductor device is symmetrically coupled to the substrate.

9. The method of claim 7, wherein a first segment and a second segment of the plurality of segments are congruent with respect to each other.

10. The method of claim 7, wherein the length of each segment of the semiconductor device is greater than or equal to 5 millimeters.

11. The method of claim 7, wherein at least one segment of the plurality of segments is a square segment.

12. The method of claim 7, wherein the semiconductor device is a semiconductor chip.