Customizable and programmable cell array

• US 6,989,687 B2
• Filed: 08/13/2004
• Issued: 01/24/2006
• Est. Priority Date: 03/10/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi
• Primary Examiner(s): LE, DON P
• Application Number:
  US10/917,396
• Publication Number:
  US 20050015699A1
• Time in Patent Office: 529 Days
• Field of Search: 326 37- 41, 257202-211
• US Class Current: 326/38
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H03K 19/1732 by limitation or reduction of the pin/gate ratio for data-processing equipment G06F1/22
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A logic array may include an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Claims

1. A method of fabricating a semiconductor device comprising:

creating a logic array comprising a multiplicity of logic cells and at least one standard metal layer, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one flip-flop and at least one inverter, said inverter having an inverter input and an inverter output, wherein said inverter input and inverter output are part of said multiplicity of inputs and multiplicity of outputs; and

customizing metal connection layers for interconnecting various ones of said inputs and outputs in a customized manner, wherein said metal layers overlay said logic array.

2. A method according to claim 1, wherein said, customizing utilizes direct write e-beam technology.

3. A method according to claim 1, wherein said standard metal layer is used at least partially for said interconnecting.

4. A method of fabricating a semiconductor device by:

creating a logic array comprising a multiplicity of cells, at least one of said cells having at least one input and at least one output, each cell including at least one flip-flop;

at least one standard metal layer; and

metal connection layers, said metal connection layers comprising at least one via layer and at least one metal layer overlying said logic array; and

customizing at least one interconnection between various inputs and outputs of said cells by customizing at least one said via layer and at least one said metal layer.

5. A method according to claim 4, wherein said step of customizing utilizes direct write e-beam technology.

6. A method according to claim 4, wherein said standard metal layer is used at least partially for said interconnection.

7. A method of fabricating a logic array comprising:

creating an array of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs;

creating at least first, second and third metal layers formed over said array of logic cells, said second metal layer comprising a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to said first axis, and said first metal layer comprising a plurality of first metal layer strips extending perpendicular to a second axis;

creating at least one via connecting at least one second metal layer strip with said first metal layer, said first metal layer underlying said second metal layer; and

customizing at least one interconnection interconnecting at least some of said multiplicity of inputs and at least some of said multiplicity of outputs, wherein said at least first, second and third metal layers are part of said interconnection.

8. A method according to claim 7, wherein said step of customizing utilizes direct write e-beam technology.

9. A method of fabricating a semiconductor device by:

creating a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one flip-flop and at least one multiplexer;

at least one standard metal layer; and

at least two metal connection layers overlying said multiplicity of logic cells; and

customizing at least one interconnection of various inputs and outputs of said logic cells, wherein at least one of said multiplexers is customized to perform a two-input logic function by said step of customizing.

10. A method according to claim 9, wherein said step of customizing utilizes direct write e-beam technology.

11. A method according to claim 9, wherein said standard metal layer is used at least partially for said interconnection.

12. A method of fabricating a semiconductor device comprising:

creating a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one flip-flop; and

at least one standard metal layer; and

customizing at least one metal connection layer overlying said logic array to interconnect various inputs and outputs of said logic cells in a customized manner, wherein at least one interconnection within a logic cell is customized by said customizing.

13. A method of fabricating a semiconductor device according to claim 12, wherein said step of customizing utilizes direct write e-beam technology.

14. A method of fabricating a semiconductor device according to claim 12, wherein said standard metal layer is used at least partially for said interconnection.

15. A method of fabricating a semiconductor device, comprising:

creating a logic array comprising a multiplicity of cells, said cells having at least one input and at least one output, each cell including at least one flip-flop, said logic array also comprising at least one standard metal layer; and

customizing interconnection of various inputs and outputs of said cells by customizing at least one via layer of metal connection layers overlaying said logic array,

wherein said standard metal layer is used at least partially for said interconnection.

16. A method of fabricating a semiconductor device according to claim 15, wherein said standard metal layer comprises at least one metal strip, said metal strip having at least two vias overlying it.

17. A method of fabricating a semiconductor device according to claim 15, wherein said standard metal layer comprises at least one metal strip, said metal strip having at least two vias underlying it.

18. A method of fabricating a semiconductor device according to claim 15, wherein said step of customizing utilizes direct write e-beam technology.