Method for application of gating signal in insulated double gate FET

• US 6,989,706 B2
• Filed: 03/25/2004
• Issued: 01/24/2006
• Est. Priority Date: 03/27/2003
• Status: Expired due to Fees

• Current Assignee: National Institute of Advanced Industrial Science and Technology (Government of Japan)
• Original Assignee: National Institute of Advanced Industrial Science and Technology (Government of Japan)
• Inventors: Koike, Hanpei, Nakagawa, Tadashi, Sekigawa, Toshihiro
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US10/808,432
• Publication Number:
  US 20040189373A1
• Time in Patent Office: 670 Days
• Field of Search: 327/333, 327/427, 327/429, 327/434, 327/437, 326/63, 326/68, 326 80- 81
• US Class Current: 327/434
• CPC Class Codes: H03K 17/302 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 3/356017 using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: H03K 3/356069 using additional transistors in the feedback circuit H03K3/356104, H03K3/3562 take precedence

Abstract

In an insulated double gate FET, the threshold voltage during the operation of a transient response thereof is enabled to be arbitrarily and accurately controlled by a method that includes applying a first input signal intended to perform an ordinary logic operation to one of the gate electrodes thereof and applying, in response to this signal, a second signal that has a signal-level temporal-change direction as the first input signal and has at least one of the low level and the high level thereof shifted by a predetermined magnitude or endowed with a predetermined time difference or has the time slower or faster signal level change of the signal to the other gate electrode.

Claims

1. A method for the application of a gating signal in an insulated double gate FET, which comprises applying, in response to a first signal fed into a first gate electrode, a second signal that has a same signal-level temporal-change direction and a same signal amplitude as the first signal and has a signal level shifted by a predetermined magnitude to a second gate electrode.

4. An integrating circuit furnished with an insulated double gate FET utilizing the method for the application of a gating signal set forth in any one of claims 1 to 3.

2. A method for the application of a gating signal in an insulated double gate FET, which comprises applying, in response to a first signal fed into a first gate electrode, a second signal that has a same signal-level temporal-change direction and a same signal amplitude as the first signal and has a slower or faster rise time or fall time to a second gate electrode.

3. A method for the application of an insulated gating signal in a double gate FET, which comprises applying, in response to a first signal fed into a first gate electrode, a second signal that has a same signal-level temporal-change direction and a same signal amplitude as the first signal and has a predetermined time difference to a second gate electrode.