Accurate power detection for a multi-stage amplifier

• US 6,989,712 B2
• Filed: 03/17/2004
• Issued: 01/24/2006
• Est. Priority Date: 11/06/2002
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Inventors: Li, Ping, Liu, Li, Souchuns, Christopher C., Henderson, Gregory N.
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US10/803,850
• Publication Number:
  US 20040174214A1
• Time in Patent Office: 678 Days
• Field of Search: 330/129, 330/133, 330/134, 330/136, 330/140
• US Class Current: 330/133
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602

Abstract

A multi-stage amplifier is coupled with a power detector. The multi-stage amplifier includes a plurality of amplifier stages in series, with a signal path extending through them. The power detector is coupled to an interior node of the amplifier along the signal path, and is operable to sample a first signal being transmitted on the signal path. The power detector outputs a second signal reflective of a power of the first signal. In one embodiment, the interior node is in a matching network of the amplifier disposed between a first amplifier stage and a final amplifier stage of the amplifier. The second signal may be used in a feedback network to adjust an amount of amplification of the first signal by the amplifier.

Claims

1. An amplifier circuit comprising:

an amplifier comprising an input, an output, and a plurality of amplifier stages coupled in series between the input and the output, wherein a signal path extends through the plurality of amplifier stages between the input and the output; and

a power detector circuit including a first input and a second input, each coupled to sample a signal transmitted along the signal path, wherein the first input is coupled to a first interior node of the signal path and the second input is coupled to a second interior node of the signal path, the first and second interior nodes being disposed between, but exclusive of, the input and the output of the amplifier, wherein the power detector circuit is operable to sample the signal transmitted along the signal path at both the first and second interior nodes, thereby creating first and second sample signals, respectively, and combine the first and second sample signals to generate a first signal reflective of both the first and second sample signals.

2. The amplifier circuit of claim 1, wherein the plurality of amplifier stages comprises:

a first amplifier stage having an input connected to the input of the amplifier;

a final amplifier stage having an output connected to the output of the amplifier; and

at least one intermediate amplifier stage coupled between the first amplifier stage and the final amplifier stage in the signal path,

wherein the first input is coupled for sampling between either the first amplifier stage and the at least one intermediate amplifier stage or between the at least one intermediate amplifier stage and the final amplifier stage.

3. The amplifier circuit of claim 2, wherein the amplifier comprises an output matching network having an input coupled to the output of the final amplifier stage and an output that forms the output of the amplifier.

4. The amplifier circuit of claim 1, wherein the amplifier includes a matching network in the signal path within the amplifier and coupled between respective ones of the plurality of amplifier stages, wherein the first interior node is within the matching network.

5. The amplifier circuit of claim 1, further comprising a bias circuit, wherein the bias circuit provides a DC bias signal to at least one of the plurality of amplifier stages, the bias signal depending, at least in part, on the first signal.

6. The amplifier circuit of claim 5, wherein the amplifier includes a matching network in the signal path within the amplifier and coupled between respective ones of the plurality of amplifier stages, wherein the first interior node is within the matching network.

7. The amplifier circuit of claim 1, wherein the plurality of amplifier stages comprises a first amplifier stage having an input connected to the input of the amplifier, the amplifier circuit further comprising a bias circuit, wherein the bias circuit provides a variable bias signal to the first amplifier stage, the bias signal depending, at least in part, on the first signal.

8. The amplifier circuit of claim 1, wherein the first signal reflects a summing of signals derived from the sampling at the at least first and second inputs.

9. The amplifier circuit of claim 1, wherein the first signal reflects a difference between signals derived from the sampling at the at least first and second inputs.

10. The amplifier circuit of claim 1, wherein the first signal reflects a greater weight given to a signal derived from the sampling at one of the first and second inputs than to a signal derived from the sampling at other of the first and second inputs.

11. An amplifier circuit comprising:

an amplifier comprising an input, an output, and a plurality of amplifier stages coupled in series between the input and the output, wherein a signal path extends through the plurality of amplifier stages between the input and the output; and

a power detector circuit including at least first and second inputs each coupled to sample a signal, wherein the first and second inputs are each coupled to the signal path at first and second interior nodes, respectively, of the amplifier, the first and second interior nodes being disposed between, but exclusive of, the input and the output of the amplifier, and the power detector circuit is operable to output a first signal reflective of the signal sampled at the at least first and second inputs.

12. The amplifier circuit of claim 11, wherein the amplifier includes a matching network in the signal path within the amplifier and coupled between respective ones of the plurality of amplifier stages, wherein the first interior node is within the matching network.

13. The amplifier circuit of claim 11, wherein the plurality of amplifier stages comprises a first amplifier stage having an input coupled to the input of the amplifier, and a second amplifier stage having an input coupled to an output of the first amplifier stage, the amplifier circuit further comprising a bias circuit, wherein the bias circuit provides a DC bias signal to at least one of the first and second amplifier stages, the bias signal depending, at least in part, on the first signal.

14. The amplifier circuit of claim 13, wherein the amplifier includes a matching network in the signal path within the amplifier and coupled between respective ones of the plurality of amplifier stages, wherein the first interior node is within the matching network.

15. The amplifier circuit of claim 11, wherein the plurality of amplifier stages comprises a first amplifier stage having an input connected to the input of the amplifier, the amplifier circuit further comprising a bias circuit, wherein the bias circuit provides a variable bias signal to the first amplifier stage, the bias signal depending, at least in part, on the first signal.

16. The amplifier circuit of claim 11, wherein the plurality of amplifier stages comprises a first amplifier stage having an input coupled to the input of the amplifier, and a second amplifier stage having an input coupled to an output of the first amplifier stage, the amplifier circuit further comprising a bias circuit, wherein the bias circuit provides a variable bias signal to the second amplifier stage, the bias signal depending, at least in part, on the first signal.

17. The amplifier circuit of claim 11, wherein the first signal reflects a summing of signals derived from the sampling at the at least first and second inputs.

18. The amplifier circuit of claim 11, wherein the first signal reflects a difference between signals derived from the sampling at the at least first and second inputs.

19. The amplifier circuit of claim 11, wherein the first signal reflects a greater weight given to a signal derived from the sampling at one of the first and second inputs than to a signal derived from the sampling at the other of the first and second inputs.

25. The amplifier circuit of claim 11, wherein the plurality of amplifier stages comprises:

a first amplifier stage having an input connected to the input of the amplifier;

a final amplifier stage having an output connected to the output of the amplifier; and

at least one intermediate amplifier stage coupled between the first amplifier stage and the final amplifier stage in the signal path, wherein the first input is coupled for sampling between either the first amplifier stage and the at least one intermediate amplifier stage or between the at least one intermediate amplifier stage and the final amplifier stage.

26. The amplifier circuit of claim 25, wherein the amplifier comprises an output matching network having an input coupled to the output of the final amplifier stage and an output that forms the output of the amplifier.

20. A method comprising:

providing an amplifier comprising an input, an output, and a plurality of amplifier stages coupled in series between the input and the output, wherein a signal path extends through the plurality of amplifier stages between the input and the output;

sampling a plurality of nodes, including sampling at an interior node within the amplifier that is between, but exclusive of, the input and output of the amplifier;

forming a first signal reflective of the sampling at the plurality of nodes, including the interior node;

providing a DC bias to at least one of the plurality amplifier stages, the DC bias being based, at least in part, on the first signal,

wherein the sampling includes sampling at a second interior node on the signal path, the second interior node being between, but exclusive of, the input and output of the amplifier.

21. The method of claim 20, wherein the first signal is formed by summing signals derived from the sampling.

22. The method of claim 20, wherein the first signal is formed based on a difference between signals derived from the sampling.

23. A method comprising:

providing an amplifier comprising an input, an output, and a plurality of amplifier stages coupled in series between the input and the output, wherein a signal path extends through the plurality of amplifier stages between the input and the output;

sampling a plurality of nodes, including sampling at an interior said node within the amplifier that is between, but exclusive of, the input and output of the amplifier;

forming a first signal reflective of the sampling at the plurality of nodes, including the interior said node;

providing a DC bias to at least one of the plurality amplifier stages, the DC bias being based, at least in part, on the first signal,

wherein the first signal is formed by summing signals derived from the sampling.

24. A method comprising:

providing an amplifier comprising an input, an output, and a plurality of amplifier stages coupled in series between the input and the output, wherein a signal path extends through the plurality of amplifier stages between the input and the output;

sampling a plurality of nodes, including sampling at an interior said node within the amplifier that is between, but exclusive of, the input and output of the amplifier;

forming a first signal reflective of the sampling at the plurality of nodes, including the interior said node;

providing a DC bias to at least one of the plurality amplifier stages, the DC bias being based, at least in part, on the first signal,

wherein the first signal is formed based on a difference between signals derived from the sampling.