Apparatus and method for testing non-deterministic device data

• US 6,990,423 B2
• Filed: 06/25/2003
• Issued: 01/24/2006
• Est. Priority Date: 06/25/2003
• Status: Active Grant

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Pane, John, Huber, Peter, Brown, Benjamin, Donahue, Mark
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): SUAREZ, FELIX E
• Application Number:
  US10/606,971
• Publication Number:
  US 20040267487A1
• Time in Patent Office: 944 Days
• Field of Search: 702/116, 702/117, 702/121, 702/179, 702/182, 702/183, 340/825.52, 370/401, 713/192, 714/43
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31932 Comparators
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

Automatic test equipment for testing non-deterministic packet data from a device-under-test is disclosed. The automatic test equipment includes a memory for storing expected packet data and a receiver for receiving the packet data from the device-under-test. A data validation circuit is coupled to the receiver for validating non-deterministic packet data based on the expected packet data from the vector memory.

Claims

1. Automatic test equipment for testing non-deterministic packet data from a device-under-test, the automatic test equipment including:

a memory for storing expected packet data;

a receiver for receiving actual packet data from the device-under-test; and

a data validation circuit coupled to the receiver for validating the non-deterministic packet data based on the expected packet data from the memory, the data validation circuit comprising a first-in-first-out circuit having an input coupled to the receiver and a match circuit having a first input coupled to the first-in-first-out circuit and a second input coupled to the memory.

2. Automatic test equipment according to claim 1 wherein the match circuit includes

a comparator operative to compare an output of the first-in-first-out circuit to the expected packet data from the memory.

3. Automatic test equipment according to claim 1, further including:

a filter having an input coupled to the memory and an output coupled to the match circuit, the filter configured to mask idle packet data or timing sequence data.

4. Automatic test equipment according to claim 1 wherein the expected packet data includes expected signatures representing valid packet data combinations from the device-under-test, the data validation circuit including:

a signature generator for generating actual signatures based upon actual packet data combinations received from the receiver; and

a comparator for comparing the actual signatures to the expected signatures to identify valid packet data.

5. Automatic test equipment according to claim 4 and further including:

a capture memory coupled to the receiver for storing the actual packet data received by the receiver.

6. Automatic test equipment according to claim 4 wherein the signature generator comprises a CRC arithmetic register.

7. Automatic test equipment according to claim 6 wherein the CRC arithmetic register comprises a linear feedback shift register.

8. Automatic test equipment for testing non-deterministic packet data from a device-under-test, the automatic test equipment including:

means for storing expected packet data;

means for receiving actual packet data from the device-under-test; and

means for validating the non-deterministic packet data based on the expected packet data from the means for storing, the means for validating comprising a first-in-first-out circuit having an input coupled to the means for receiving and a match circuit having a first input coupled to the first-in-first-out circuit and a second input coupled to the means for storing.

9. Automatic test equipment according to claim 8 wherein the match circuit includes

a comparator operative to compare an output of the first-in-first-out circuit to the expected packet data from the means for storing expected packet data.

10. Automatic test equipment according to claim 8 wherein the means for storing expected packet data includes means for storing expected signatures representing valid packet data combinations from the device-under-test, the means for validating including:

means for generating a signature based upon actual packet data combinations received from the receiver; and

means for comparing the actual signatures to the expected signatures to identify valid packet data.

11. Automatic test equipment according to claim 8 and further including:

means for capturing the actual packet data from the receiver.

12. Automatic test equipment according to claim 10 wherein the means for generating a signature includes:

a CRC arithmetic register.

13. Automatic test equipment according to claim 12 wherein the CRC arithmetic register comprises:

a linear feedback shift register.

14. A method for testing non-deterministic packet data using automatic test equipment having a memory for storing expected packet data, the method comprising:

receiving actual packet data from a device-under-test;

sequencing the actual packet data through a first-in-first out circuit;

comparing, in the order received, each actual packet data to the expected packet data in the memory; and

validating the non-deterministic packet data based on the comparing step.

15. A method according to claim 14 wherein the expected packet data includes idle data or timing sequence data, the method further comprising:

filtering the idle data or timing sequence data to generate filtered expected data, and wherein the comparing step includes comparing, in the order received, each actual packet data to the filtered expected packet data.

16. A method according to claim 14 wherein the memory stores expected signatures representing valid packet data combinations from the device-under-test, the method further comprising:

generating an actual signature for each actual data packet, wherein the comparing step includes comparing the generated actual signature to the expected signatures and

the validating step includes determining whether the actual data packet passed or failed based on the comparison of the actual and expected signatures.

17. A method according to claim 16 wherein the step of generating an actual signature includes:

calculating a checksum from the actual packet data.

18. A method for validating non-deterministic packet data from a device-under-test using automatic test equipment, the automatic test equipment having a memory, the method comprising:

establishing a library of known signatures in the memory, wherein the known signatures are passing signatures, failing signatures or both;

testing the device-under-test;

generating a signature of actual packet data captured during the testing step;

comparing the generated signature from the captured data to the library of known signatures;

determining a pass/fail result for the device test if the compared signature matches at least one known signature in the library;

evaluating the captured data to determine whether the device passed/failed if the compared signature does not match at least one known signature in the library;

generating a new signature for the evaluated captured data; and

adding the new signature to the library of known signatures.