Method for error detection/correction of multilevel cell memory and multilevel cell memory having error detection/correction function

• US 6,990,623 B2
• Filed: 05/16/2002
• Issued: 01/24/2006
• Est. Priority Date: 05/16/2001
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Fujitsu Limited
• Inventors: Furukawa, Hideyuki
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US10/146,074
• Publication Number:
  US 20030061560A1
• Time in Patent Office: 1,349 Days
• Field of Search: 714/773
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: H03M 13/11 using multiple parity bits

Abstract

Binary bit addresses for error detection designating the individual bits of multilevel memory cells for retaining two bits of data, respectively, are assigned so that pairs of the binary bit addresses corresponding to each of the memory cells are mutually exclusive in each digit. For each digit of the binary bit addresses, first parity codes including a parity code of data corresponding to all the binary bit addresses having “0” in the digit and a parity code of data corresponding to all the binary bit addresses having “1” in the digit are generated for both write data and read data. The presence of a memory cell storing erroneous data in both bits is detected when all the first parity codes of the read data are different from the first parity codes of the write data. Thus, the multilevel cell memory can perform reliable error detection/correction by a simple method.

Claims

1. A method for error detection/correction of a multilevel cell memory having memory cells each for retaining two bits of data, the method comprising the steps of:

assigning binary bit addresses, for error detection, said binary bit addresses designating individual bits of said memory cells such that each pair of said binary bit addresses corresponding to each of said memory cells is mutually exclusive in each digit;

generating, for each digit of said binary bit addresses, first parity codes including a parity code of write data corresponding to all of said binary bit addresses having “

0”

in said digit and a parity code of said write data corresponding to all of said binary bit addresses having “

1”

in said digit;

generating first parity codes of read data corresponding to said binary bit addresses whose combinations are the same as used in the generation of said first parity codes of said write data, when reading data from said memory cells; and

detecting a presence of one memory cell storing erroneous data in both bits when said first parity codes generated in the read operation are all different from said first parity codes generated in the write operation.

2. The method for error detection/correction of a multilevel cell memory according to claim 1, further comprising the steps of:

assigning binary cell addresses, for error correction, designating said individual memory cells;

generating, for each digit of said binary cell addresses, a second parity code of data to be written to all memory cells with binary cell addresses having a selected value in said digit;

generating a second parity code of data read from said either of bits of said memory cells corresponding to said binary cell addresses whose combinations are the same as used in the generation of said second parity code of said write data when a presence of one memory cell storing erroneous data in both bits is detected;

obtaining exclusive ORs of individual bits of said second parity code generated in said write operation and individual bits of said second parity code generated in said read operation;

determining a binary cell address having an error by assigning the obtained exclusive ORs to designate respective digits of the address; and

correcting the error by inverting two bits of data read from said memory cell having the error.

3. The method for error detection/correction of a multilevel cell memory according to claim 1, further comprising the steps of:

obtaining exclusive ORs of said first parity codes generated in said write operation and said first parity codes generated in said read operation;

detecting that data read from said memory cells includes a single-bit error when pairs of said exclusive ORs corresponding to complementary for each of said digits concerned at the generation of said first parity codes have complementary values;

determining a binary bit address having an error by assigning either exclusive OR of each of said pairs of exclusive ORs to designated a respective digit of the address; and

correcting the error by inverting data corresponding to the determined binary bit address among said data read from said memory cells.

4. A multilevel cell memory having an error detection/correction function, comprising:

a plurality of memory cells each for retaining two bits of data;

a first generating circuit for

assigning binary bit addresses, for error detection, designating individual bits of said memory cells, such that each pair of said binary bit addresses corresponding to each of said memory cells is mutually exclusive in each digit,

generating, for each digit of said binary bit addresses, first parity codes including a parity code of write data corresponding to all of said binary bit addresses having “

0”

in said digit and a parity code of said write data corresponding to all of said binary bit addresses having “

1”

in said digit, and

generating first parity codes of read data corresponding to said binary bit addresses whose combinations are the same as used in the generation of said first parity codes of said write data, when reading data from said memory cells; and

a first detecting circuit for detecting a presence of one memory cell storing erroneous data in both bits when said first parity codes generated in the read operation are all different from said first parity codes generated in the write operation.

5. The multilevel cell memory having an error detection/correction function according to claim 4, further comprising:

a converting circuit for converting each bit of said first parity codes into two-bit data; and

multilevel memory cells each for retaining said first parity codes as said two-bit data.

6. The multilevel cell memory having an error detection/correction function according to claim 4, further comprising:

a second generating circuit for

assigning binary cell addresses, for error correction, to designating said individual memory cells,

generating, for each digit of said binary cell addresses, a second parity code of data to be written to memory cells with binary cell addresses having a selected value in said digit, and

generating a second parity code of data read from said memory cells corresponding to said binary cell addresses whose combinations are the same as used in the generation of said second parity code of said write data, when a presence of one memory cell storing erroneous data in both bits is detected; and

a first correcting circuit for

obtaining exclusive ORs of individual bits of said second parity code generated in said write operation and individual bits of said second parity code generated in said read operation,

determining a binary cell address having an error by assigning the obtained exclusive ORs to designate respective digits of the address, and

correcting the error by inverting two bits of data read from said one memory cell having the error.

7. The multilevel cell memory having an error detection/correction function according to claim 6, further comprising:

a converting circuit for converting each bit of said second parity codes into two-bit data; and

multilevel memory cells each for retaining said second parity codes as said two-bit data.

8. The multilevel cell memory having an error detection/correction function according to claim 4, further comprising:

a second detecting circuit for

obtaining exclusive ORs of said first parity codes generated in said write operation and said first parity codes generated in said read operation, and

detecting that data read from said memory cells includes a single-bit error when pairs of said exclusive ORs corresponding to complementary values of each digit concerned at the generation of said first parity codes all have complementary values; and

a second correcting circuit for

determining a binary bit address having an error by assigning either exclusive OR of each of said pairs of exclusive ORs to designate respective digit of the binary bit address, and

correcting the error by inverting data corresponding to the determined binary bit address among said data read from said memory cells.

9. A method for error detection/correction of a multilevel cell memory having memory cells each for retaining a plurality of bits of data, the method comprising the steps of:

constituting a plurality of first groups by selecting two bits from each of said memory cells as a bit pair; and

,

for each of said first groups,

assigning two binary first addresses designating each bit of the bit pair for each of said memory cells such that said two binary first addresses are mutually exclusive in each digit,

generating, for each digit of said binary first addresses, first parity codes including a parity code of write data corresponding to all of said binary first addresses having “

0”

in said digit and a parity code of said write data corresponding to all of said binary first addresses having “

1”

in said digit,

generating first parity codes of read data corresponding to said binary first addresses whose combinations are the same as used in the generation of said first parity codes of said write data, when reading data from said memory cells, and

detecting a presence of one memory cell storing erroneous data in both bits of a bit pair thereof in an area allocated to each of said first groups when said first parity codes generated in the read operation are all different from said first parity codes generated in the write operation.

10. The method for error detection/correction of a multilevel cell memory according to claim 9, further comprising the steps of:

constituting a plurality of second groups different from said first groups by selecting bits in combinations of said bit pairs defined for the first groups;

for each of said second groups,

assigning binary second addresses, for error correction designating the bit pairs in individual memory cells, and

generating, for each digit of said binary second addresses, second parity codes of write data corresponding to all of said binary second addresses having “

0”

in said digit or second parity codes of said write data corresponding to all of said binary first addresses having “

1”

in said digit; and

,

for each of said second groups,

generating second parity codes of data read from said memory cells corresponding to said binary second addresses whose combinations are the same as used in the generation of said second parity codes of said write data,

obtaining exclusive ORs of said second parity codes generated in the write operation and said second parity codes generated in the read operation when a presence of one memory cell storing erroneous data in both bits of a bit pair thereof is detected,

determining a binary second address having an error by assigning the obtained exclusive ORs to designate respective digits of the binary second address, and

correcting the error by inverting two bits of data read from said one memory cell having the error.

11. The method for error detection/correction of a multilevel cell memory according to claim 9, further comprising the steps of,

for each of said first groups:

obtaining exclusive ORs of said first parity codes generated in the write operation and said first parity codes generated in the read operation;

detecting that data read from said memory cells includes a single-bit error when pairs of the exclusive ORs corresponding to each of the address digits concerned at the generation of the first parity codes are all inverted from each other;

determining a binary first address having an error by assigning one of each of said pairs of exclusive ORs to designate respective digits of the binary first address; and

correcting the error by inverting data corresponding to the determined binary first address among said data read from said memory cells.

12. The method for error detection/correction of a multilevel cell memory according to claim 9, further comprising the steps of,

for each of said first groups:

obtaining exclusive ORs of said first parity codes generated in the write operation and said first parity codes generated in the read operation; and

detecting that said first parity codes include a single-bit error when only one of the exclusive ORs is “

1”

.

13. A multilevel cell memory having an error detection/correction function, comprising:

a plurality of memory cells each for retaining a plurality of bits of data;

a plurality of first groups each being constituted by selecting one of two bits from each of said memory cells;

a first generating circuit for

assigning two binary first addresses respectively designating one bit of each bit pair of said memory cells for each of said first groups such that said two binary first addresses are mutually exclusive in each digit,

generating, for each digit of said binary first addresses, first parity codes including a parity code of write data corresponding to all of said binary first addresses having “

0”

in said digit and a parity code of said write data corresponding to all of said binary first addresses having “

1”

in said digit, for each of said first groups, and

generating, for each of said first groups, first parity codes of read data corresponding to said binary first addresses whose combinations are the same as used in the generation of said first parity codes of said write data, when reading data from said memory cells; and

a first detecting circuit for detecting, for each of said first groups, a presence of one memory cell storing erroneous data in both bits of a bit pair thereof in an area allocated to each of said first groups when said first parity codes generated in the read operation are all different from said first parity codes generated in the write operation.

14. The multilevel cell memory having an error detection/correction function according to claim 13, further comprising:

a plurality of second groups independent of said first groups and each being constituted by selecting combinations of both bits of said bit pairs of the respective first groups;

a second generating circuit for

assigning binary second addresses, for error correction, designating the individual memory cells, for each of said second groups,

generating, for each digit of said binary second addresses, second parity codes of write data corresponding to all of said binary second addresses having “

0”

in said digit or second parity codes of said write data corresponding to all of said binary second addresses having “

1”

in said digit, and

generating, second parity codes of data read from said memory cells corresponding to said binary second addresses whose combinations are the same as used in the generation of said second parity codes of said write data; and

a first correcting circuit for

obtaining, when one memory cell storing erroneous data in both bits of a bit pair thereof is detected, exclusive ORs of individual bits of said second parity codes generated in the write operation and individual bits of said second parity codes generated in the read operation,

determining a binary second address having an error by assigning the obtained exclusive ORs to designate respective digits of the binary second address, and

correcting the error by inverting two bits of data read from said one memory cell having the error.

15. The multilevel cell memory having an error detection/correction function according to claim 13, further comprising:

a second detecting circuit for

obtaining, for each of said first groups, exclusive ORs of said first parity codes generated in the write operation and said first parity codes generated in the read operation, and

detecting, for each of said first groups, that in the area allocated to each of said first groups data read from said memory cells includes a single-bit error when all pairs of exclusive ORs corresponding to complementary values for each of said address digits concerned at the generation of said first parity codes are all inverted from each other; and

a second correcting circuit for

determining, for each of said first groups having a single-bit error detected, a binary first address having the detected error by assigning either exclusive OR of said pairs of exclusive ORs to designate respective digits of the address; and

correcting the error for each of said first groups by inverting data corresponding to the determined binary first address among said data read from said memory cells.

16. The multilevel cell memory having an error detection/correction function according to claim 13, further comprising a third detecting circuit for obtaining, for each of said first groups, exclusive ORs of said first parity codes generated in the write operation and said first parity codes generated in the read operation, and for detecting that said first parity codes include a single-bit error when only one of the exclusive ORs is “

1”

.

17. The multilevel cell memory having an error detection/correction function according to claim 13, further comprising a parity memory circuit having a plurality of multilevel memory cells for storing said first parity codes, respectively, wherein

said first parity codes are simultaneously stored into a plurality of bits of the respective multilevel memory cells in said parity memory circuit.