Method for static timing verification of integrated circuits having voltage islands
First Claim
1. A method of analysis of an integrated circuit design having multiple voltage islands, comprising:
- (a) determining a clock path through said voltage islands;
(b) determining a data path through said voltage islands;
(c) determining which said voltage islands are independent voltage islands;
(d) determining which said voltage islands are dependent voltage islands;
(e) for said data path and said clock path, performing a worst case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in said data and clock paths; and
(f) for said data path and said clock path, performing a best case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in said data and clock paths.
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Abstract
A method of analysis of an integrated circuit design having multiple voltage islands, including: (a) determining a clock path through the voltage islands; (b) determining a data path through the voltage islands; (c) determining which voltage islands are independent voltage islands; (d) determining which voltage islands are dependent voltage islands; (e) for the data path and the clock path, performing a worst case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths; and (f) for the data path and the clock path, performing a best case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths.
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Citations
30 Claims
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1. A method of analysis of an integrated circuit design having multiple voltage islands, comprising:
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(a) determining a clock path through said voltage islands; (b) determining a data path through said voltage islands; (c) determining which said voltage islands are independent voltage islands; (d) determining which said voltage islands are dependent voltage islands; (e) for said data path and said clock path, performing a worst case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in said data and clock paths; and (f) for said data path and said clock path, performing a best case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in said data and clock paths. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for analysis of an integrated circuit design having multiple voltage islands said method steps comprising:
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(a) determining a clock path through said voltage islands; (b) determining a data path through said voltage islands; (c) determining which said voltage islands are independent voltage islands; (d) determining which said voltage islands are dependent voltage islands; (e) for said data path and said clock path, performing a worst case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in said data and clock paths; and (f) for said data path and said clock path, performing a best case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in said data and clock paths. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A computer system comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to communicate with said processor, said memory unit containing instructions that when executed implement a method for analysis of an integrated circuit design having multiple voltage islands, said method comprising the computer implemented steps of:
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(a) determining a clock path through said voltage islands; (b) determining a data path through said voltage islands; (c) determining which said voltage islands are independent voltage islands; (d) determining which said voltage islands are dependent voltage islands; (e) for said data path and said clock path, performing a worst case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in said data and clock paths; and (f) for said data path and said clock path, performing a best case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in said data and clock paths. - View Dependent Claims (26, 27, 28, 29, 30)
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Specification