Method for forming a semiconductor structure with improved smaller forward voltage loss and higher blocking capability

• US 6,991,977 B2
• Filed: 09/18/2003
• Issued: 01/31/2006
• Est. Priority Date: 10/17/2001
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher Boguslaw
• Primary Examiner(s): Pham, Long
• Application Number:
  US10/666,034
• Publication Number:
  US 20040063269A1
• Time in Patent Office: 866 Days
• Field of Search: 438/197, 438/206, 438/212, 438/268
• US Class Current: 438/206
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device is formed as follows. A semiconductor substrate having a first region of a first conductivity type is provided. A region of a second conductivity type is formed in the semiconductor substrate such that the first and second regions form a p-n junction. First and second charge control electrodes are formed adjacent to but insulated from one of the first and second regions, along a dimension parallel to flow of current through the semiconductor device, wherein the first charge control electrode is adapted to be biased differently than the second charge control electrode.

Claims

1. A method for forming a semiconductor device, the method comprising:

providing a semiconductor substrate having a first region of a first conductivity type;

forming a second region of a second conductivity type in the semiconductor substrate such that the first and second regions form a p-n junction; and

forming first and second charge control electrodes adjacent to but insulated from one of the first and second regions, along a dimension parallel to flow of current through the semiconductor device, wherein the first charge control electrode is adapted to be biased differently than the second charge control electrode.

3. The method of claim 1 further comprising:

forming a trenched gate structure in the semiconductor substrate.

4. The method of claim 1 wherein the first and second charge control electrodes comprise polysilicon.

5. The method of claim 1 wherein the method further comprises forming a plurality of biasing elements on or in the semiconductor substrate, wherein the biasing elements are adapted to bias the first and second charge control electrodes at different voltages.

6. The method of claim 1 wherein the semiconductor device is a power MOSFET.

2. A method for forming a semiconductor device, the method comprising:

providing a semiconductor substrate having a first region of a first conductivity type;

forming a second region of a second conductivity type in the semiconductor substrate;

forming a trench in the semiconductor substrate;

forming a first charge control electrode in the trench by depositing a conductive material in the trench and then etching the deposited conductive material; and

forming a second charge control electrode in the trench by depositing a conductive material in the trench and then etching the deposited conductive material, wherein the first charge control electrode is adapted to be biased differently than the second charge control electrode.

7. A method for forming a field effect transistor comprising:

a) providing a semiconductor substrate of a first conductivity type having a major surface, a drift region, and a drain region;

b) forming a well region of a second conductivity type in the semiconductor substrate;

c) forming a source region of the first conductivity type in the well region;

d) forming a source contact layer on the source region;

e) forming a gate electrode adjacent to the source region;

f) forming a charge control electrode in the drift region, wherein the charge control electrode is adapted to be biased at a different potential than the gate electrode or the source contact layer, and is adapted to control the electric field in the drift region; and

g) forming a dielectric material around the charge control electrode.

8. The method of claim 7 wherein the gate electrode is a trenched gate electrode.

9. The method of claim 7 further comprising:

forming a biasing element, wherein the biasing element is adapted to bias the charge control electrode.