Integrated circuit devices with metal-insulator-metal capacitors

• US 6,992,346 B2
• Filed: 03/23/2004
• Issued: 01/31/2006
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Han-Mei, Kim, Young-Sun, Lim, Jae-Soon, Kim, Ki-Chul, Nam, Gab-Jin, Kim, Sung-Tae, Kwon, Thomas Jongwan
• Primary Examiner(s): Ngô, Ngân V.
• Assistant Examiner(s): Nguyen, Thinh T
• Application Number:
  US10/807,000
• Publication Number:
  US 20040262661A1
• Time in Patent Office: 679 Days
• Field of Search: 257/303, 257/306, 257/304
• US Class Current: 257/303
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A conductive contact plug extends through an opening in the dielectric layer to contact the substrate and includes a widened pad portion extending onto the dielectric layer adjacent the opening. An ohmic pattern is disposed on the pad portion of the plug, and a barrier pattern is disposed on the ohmic pattern. A concave first capacitor electrode is disposed on the barrier pattern and defines a cavity opening away from the substrate. A capacitor dielectric layer conforms to a surface of the first capacitor electrode and a second capacitor electrode is disposed on the capacitor dielectric layer opposite the first capacitor electrode. Sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug may be substantially coplanar, and the device may further include an etch stopper layer conforming to at least sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug. Related fabrication methods are described.

Claims

1. An integrated circuit device comprising:

a microelectronic substrate;

a dielectric layer on the substrate;

a conductive contact plug extending through an opening in the dielectric layer to contact the substrate and including a widened pad portion extending onto the dielectric layer adjacent the opening;

an ohmic pattern on the pad portion of the plug;

a barrier pattern on the ohmic pattern;

a concave first capacitor electrode disposed on the barrier pattern and defining a cavity opening away from the substrate;

a capacitor dielectric layer conforming to a surface of the first capacitor electrode; and

a second capacitor electrode disposed on the capacitor dielectric layer opposite the first capacitor electrode.

2. A device according to claim 1, wherein sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug are substantially coplanar.

3. A device according to claim 2, comprising an etch stopper layer conforming to at least sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug.

4. A device according to claim 3, wherein the etch stopper layer also overlies a top surface of the barrier pattern.

5. A device according to claim 3, wherein the etch stopper layer comprises a dielectric material having an etch selectivity with respect to at least material of a group including Hydrogen Silsesquioxane (HSQ), Boron Phosphorus Silicate Glass (BPSG), High density plasma (HDP) oxide, plasma enhanced tetraethyl orthosilicate (PETEOS), Undoped Silicate Glass (USG), Phosphorus Silicate Glass (PSG), plasma-enhanced (PE)-SiH₄ and aluminum oxide (Al₂O₃).

6. A device according to claim 5, wherein the etch stopper layer comprises at least one material from a group including silicon nitride (Si₃N₄) and tantalum oxide (Ta₂O₅).

7. A device according to claim 1, wherein the contact plug comprises polysilicon.

8. A device according to claim 1, wherein the ohmic pattern comprises titanium silicide (TiSi_x).

9. A device according to claim 1, wherein the barrier pattern comprises at least one material from a group including titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN) and titanium aluminum nitride (TiAlN).

10. A device according to claim 1, wherein the first electrode and the second electrode each comprise at least one material from a group including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), platinum (Pt), iridium (Ir), osmium (Os), rhodium (Rh), cobalt (Co) and nickel (Ni).

11. A device according to claim 1, further comprising a metal etch stopper pattern interposed between the first capacitor electrode and the barrier pattern.

12. A device according to claim 1, further comprising a support layer disposed on the dielectric layer and laterally abutting a base of the concave first capacitor electrode.

23. A device according to claim 1, wherein a portion of the contact plug extending through the opening in the dielectric layer to contact the substrate and the widened pad portion form a continuous material region.

24. A device according to claim 23, wherein the continuous material region comprises polysilicon.

27. A device according to claim 1, further comprising a resistor on the dielectric layer, wherein the resistor includes a first layer made of the same material as the conductive plug, a second layer made of the same material as the ohmic pattern, and a third layer made of the same material as the barrier pattern, sequentially stacked on the dielectric layer.

13. An integrated circuit device comprising:

a microelectronic substrate;

a dielectric layer on the substrate;

a conductive contact plug extending through an opening in the dielectric layer to contact the substrate and including a widened pad portion extending onto the dielectric layer adjacent the opening;

stacked ohmic and barrier patterns disposed on the pad portion of the plug and having sidewalls substantially coplanar with a sidewall of the pad portion;

a first capacitor electrode disposed on the barrier pattern;

a capacitor dielectric layer on the first capacitor electrode; and

a second capacitor electrode on the capacitor dielectric layer opposite the first capacitor electrode.

14. A device according to claim 13, further comprising an etch stopper layer conforming to at least the sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug.

15. A device according to claim 14, wherein the etch stopper layer also overlies a portion of the barrier pattern.

16. A device according to claim 14, wherein the etch stopper layer comprises a dielectric material having an etch selectivity with respect to at least one material from a group including Hydrogen Silsesquioxane (HSQ), Boron Phosphorus Silicate Glass (BPSG), High density plasma (HDP) oxide, plasma enhanced tetraethyl orthosilicate (PETEOS), Undoped Silicate Glass (USG), Phosphorus Silicate Glass (PSG), plasma-enhanced (PE)-SiH₄ and aluminum oxide (Al₂O₃).

17. A device according to claim 16, wherein the etch stopper layer comprises at least one material from a group including silicon nitride (Si₃N₄) and tantalum oxide (Ta₂O₅).

18. A device according to claim 13, wherein the contact plug comprises polysilicon.

19. A device according to claim 13, wherein the ohmic pattern comprises titanium silicide (TiSi_x).

20. A device according to claim 13, wherein the barrier pattern comprises at least one material from a group including titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN) and titanium aluminum nitride (TiAlN).

21. A device according to claim 13, wherein the first electrode and the second electrode each comprise at least one material from a group including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), platinum (Pt), iridium (Ir), osmium (Os), rhodium (Rh), cobalt (Co) and nickel (Ni).

22. A device according to claim 13, further comprising a metal etch stopper pattern interposed between the first capacitor electrode and the barrier pattern.

25. A device according to claim 13, wherein a portion of the contact plug extending through the opening in the dielectric layer to contact the substrate and the widened pad portion form a continuous material region.

26. A device according to claim 25, wherein the continuous material region comprises polysilicon.

28. A device according to claim 13, further comprising a resistor on the dielectric layer, wherein the resistor includes a first layer made of the same material as the conductive plug, a second layer made of the same material as the ohmic pattern, and a third layer made of the same material as the barrier pattern, sequentially stacked on the dielectric layer.