Trenched DMOS devices and methods and processes for making same

• US 6,992,352 B2
• Filed: 05/20/2003
• Issued: 01/31/2006
• Est. Priority Date: 05/15/2003
• Status: Expired due to Fees

• Current Assignee: Analog Power Limited
• Original Assignee: Analog Power Limited
• Inventors: Sin, Johnny Kin On, Lai, Tommy Mau Lam
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): LOUIE, WAI SING
• Application Number:
  US10/441,018
• Publication Number:
  US 20040232482A1
• Time in Patent Office: 987 Days
• Field of Search: 257/332, 257/335, 257/339, 257/401, 257/409, 257/491, 257/500, 257/341, 257/50
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention describes a process for making a high density trench DMOS (Double-diffused Metal Oxide Semiconductor) transistor with improved gate oxide breakdown at the three-dimensional trench corners and better body contact which can improve the latch-up immunity and increase the drive current. A guard-ring mask is used to define a deep body to cover the three-dimensional trench corners, which can prevent early gate-oxide breakdown during the off-state operation. Another function of the guard-ring mask is to define self-aligned deeper trenches at the terminations of the trenches. The deeper trenches at the terminations of the trenches will result in thicker gate oxide grown at the terminations. This layer of thicker oxide is used to prevent the pre-mature gate oxide breakdown at the three-dimensional trench corners. A trench spacer is formed after the N-body drive-in step by depositing a layer of oxide and then followed by an oxide etch-back step. This spacer is used to prevent any unwanted impurities to penetrate through the trench sidewall and get into the device channel during the high dosage source implantation step.

Claims

1. A DMOS semiconductor device including a plurality of DMOS transistor cells, each said DMOS transistor cell being formed on a substrate of a first conductivity type and including a body-region of a second conductivity type, said transistor cell including a trench formed on said substrate, said trench having a first longitudinal end, a second longitudinal end and a middle portion interconnecting said first longitudinal end and said second longitudinal end, with a bottom surface of said first and second longitudinal ends being depressed below the bottom surface of said middle portion of said trench, said elongated trench being covered with a layer of insulating substance with said layer of insulating substance at said first and second longitudinal ends of said trench being thicker than along said middle portion of said trench.

2. A DMOS semiconductor device of claim 1, wherein said layer of insulating substance is sandwiched between a layer of conductive substance and the bottom and side surfaces of said trench.

3. A DMOS semiconductor device of claim 2, wherein said conductive substance includes polysilicon and said insulating substance includes an insulative oxide, nitride or like substance.

4. A DMOS semiconductor device of claim 2, wherein the thickness of said layer of insulating substance at said first and second longitudinal ends of said trench exceeds that of the shallower middle portion of said trench by at least 400 Å

.

5. A DMOS device of claim 4, wherein a first and a second islands are formed respectively adjacent to said first and said second ends of said trench, said trench being intermediate of said first and said second islands.

6. A DMOS device of claim 5, wherein said first and said second islands protrude above said trench and said body-region.

9. A device of claim 1, wherein said first and said second ends of said trench being at least about 400Å

deeper than the depth of the shallower middle portion of said trench.

7. A DMOS semiconductor device comprising a plurality of DMOS transistor cells, each said DMOS transistor cell being formed on a substrate of a first conductivity type and comprising a body-region of a second conductivity type, said DMOS transistor cell including a trench formed on said substrate and having a first longitudinal end, a second longitudinal end and a middle portion interconnecting said first and said second longitudinal ends, the bottom surface of said first and second longitudinal ends being depressed below the bottom surface of said middle portion of said trench, said trench being covered with a layer of insulating substance sandwiched between a layer of conductive substance and the bottom and side surfaces of said trench, the layer of insulating substance at said first and second longitudinal ends of said trench being thicker than along said middle portion of said trench, the thickness of said layer of insulating substance at said first and second longitudinal ends of said trench exceeds that of the shallower middle portion of said trench by at least 400Å

, first and second islands formed respectively adjacent first and said second longitudinal ends of said trench, said trench being intermediate said first and said second islands, wherein said first and said second islands are separated from said trench by said body-region.

8. A DMOS semiconductor device comprising a plurality of DMOS transistor cells, each said DMOS transistor cell being formed on a substrate of a first conductivity type and comprising a body-region of a second conductivity type, said DMOS transistor cell including a trench formed on said substrate and having a first longitudinal end, a second longitudinal end and a middle portion interconnecting said first and said second longitudinal ends, the bottom surface of said first and second longitudinal ends being depressed below the bottom surface of said middle portion of said trench, said trench being covered with a layer of insulating substance sandwiched between a layer of conductive substance and the bottom and side surfaces of said trench, the layer of insulating substance at said first and second longitudinal ends of said trench being thicker than along said middle portion of said trench, the thickness of said layer of insulating substance at said first and second longitudinal ends of said trench exceeds that of the shallower middle portion of said trench by at least 400Å

, first and second islands formed respectively adjacent first and said second longitudinal ends of said trench, said trench being intermediate said first and said second islands, wherein said first and said second islands are formed from an insulating oxide.