Method circuit and system for read error detection in a non-volatile memory array

• US 6,992,932 B2
• Filed: 10/29/2003
• Issued: 01/31/2006
• Est. Priority Date: 10/29/2002
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Cohen, Guy
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/695,457
• Publication Number:
  US 20040136236A1
• Time in Patent Office: 825 Days
• Field of Search: 365/185.03, 365/185.2, 365/185.21, 365/185.22
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

The present invention is a method, circuit and system for determining a reference voltage to be used in reading cells programmed to a given program state. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used in operating (e.g. reading) cells in a NVM block or array. As part of the present invention, at least a subset of cells of the NVM block or array may be read and the number of cells found at a given state associated with the array may be compared to one or more check sum values obtained during programming of the at least a subset of cells. A Read Verify threshold reference voltage associated with the given program state or associated with an adjacent state may be adjusted based on the result of the comparison.

Claims

1. A method of detecting read errors in a set of NVM cells, said method comprising:

during or prior to programming of the set of NVM cells, counting the number of cells to be programmed to, up to and/or above one or more logical states of a set of logical states associated with the NVM cells; and

comparing the number of cells read at a given state against a value corresponding to a number of cells which should be at the given state based on the counting performed during or prior to programming.

2. The method according to claim 1, wherein counting comprises counting the number of NVM cells to be programmed at or above each logical state associated with the set of cells.

3. The method according to claim 1, wherein comparing comprises comparing the number of cells read at a given state to the number of cells of the set which were programmed at or above the given state and the number of cells of the set which were programmed at or above a logical state adjacent to and higher than the given state.

4. The method according to claim 3, further comprising determining the number of cells which should be at the given state by subtracting the number of cells of the set which were programmed at or above the given state by the number of cells of the set which were programmed at or above a higher adjacent state to the given state.

5. A method of adjusting one or more read verify reference levels of a set of cells comprising:

during or prior to programming of the set of cells, counting the number of cells to be programmed to, up to and/or above one or more logical states of a set of logical states associated with the set of NVM cells;

comparing the number of cells read at a given state against a value corresponding to a number of cells which should be at the given state based on the counting performed during or prior to programming; and

either raising or lowering a read verify level associate with the given state, or associated with an adjacent state, based on the comparison.

6. The method according to claim 5, wherein counting comprises counting the number of cells to be programmed at or above each logical state associated with the set of cells, comparing comprises comparing the number of cells read at a given state to the number of cells of the set which were programmed at or above the given state and the number of cells of the set which were programmed at or above a logical state adjacent to and higher than the given state.

7. The method according to claim 6, wherein if the number of cells read at a given logical state is lower than the number of cells expected at the given state, either the read verify level associated with that given state may be lowered or the read verify level of the adjacent higher state may be raised.

8. The method according to claim 6, wherein if the number of cells read at a given logical state is greater than the number of cells expected at the given state, either the read verify level associated with that given state may be raised or the read verify level of the adjacent higher state may be lowered.