Analog unidirectional serial link architecture
First Claim
1. A unified serial link system comprising a transmitter portion and a receiver portion, said transmitter portion further comprising:
- a transmitter phase locked loop control circuit;
a transmitter phase buffer circuit connected to the transmitter phase locked loop control circuit;
a transmitter equalization driver circuit connected to said phase buffer circuit; and
said receiver portion further comprising;
a receiver phase locked loop control circuit;
a receiver phase rotator circuit connected to the receiver phase locked loop control circuit; and
a receiver phase buffer circuit connected to the receiver phase rotator circuit;
wherein the receiver phase rotator circuit is configured to acquire a clock phase from the receiver phase locked loop control circuit and modulo shift the clock phase into a desired phase angle.
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Accused Products
Abstract
A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver. The system comprises a phase locked loop (PLL) control circuit, a phase rotator circuit, a phase buffer circuit, and an equalization driver circuit. The phase rotator circuit is configured to acquire a clock phase from the phase locked loop control circuit and modulo shift the clock phase into a desired phase angle. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop, a multi-stage voltage controlled oscillator, a voltage comparator, a PLL control logic, a digital to analog counter and a low pass filter. The fine loop includes the oscillator, a frequency divider, a phase-frequency detector, a charge pump and a loop filter.
31 Citations
18 Claims
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1. A unified serial link system comprising a transmitter portion and a receiver portion, said transmitter portion further comprising:
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a transmitter phase locked loop control circuit; a transmitter phase buffer circuit connected to the transmitter phase locked loop control circuit; a transmitter equalization driver circuit connected to said phase buffer circuit; and said receiver portion further comprising; a receiver phase locked loop control circuit; a receiver phase rotator circuit connected to the receiver phase locked loop control circuit; and a receiver phase buffer circuit connected to the receiver phase rotator circuit; wherein the receiver phase rotator circuit is configured to acquire a clock phase from the receiver phase locked loop control circuit and modulo shift the clock phase into a desired phase angle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for providing a unified serial link comprising the steps of:
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a. providing a receiver phase locked loop control circuit; b. the receiver phase locked loop control circuit generating a clock phase; c. connecting a receiver phase rotator circuit to the receiver phase locked loop control circuit; d. the receiver phase rotator circuit receiving the clock phase from the receiver phase locked loop control circuit; e. the receiver phase rotator circuit modulo shifting the clock phase into a desired phase angle; f. connecting a receiver phase buffer circuit to the receiver phase rotator circuit; g. the receiver phase buffer circuit buffering the phase angle; h. providing a transmitter phase locked loop control circuit; i. connecting a transmitter phase buffer circuit to the transmitter phase locked loop control circuit; and i. connecting a transmitter equalization driver to the transmitter phase buffer circuit. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification