Zero-delay buffer circuit for a spread spectrum clock system and method therefor

• US 6,993,109 B2
• Filed: 08/30/2002
• Issued: 01/31/2006
• Est. Priority Date: 11/18/1999
• Status: Expired due to Term

• Current Assignee: AnaPass, Inc.
• Original Assignee: AnaPass, Inc.
• Inventors: Lee, Kyeongho, Park, Joonbae
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): ODOM, CURTIS B
• Application Number:
  US10/231,312
• Publication Number:
  US 20030169086A1
• Time in Patent Office: 1,250 Days
• Field of Search: 375130-153, 375371-376, 327/105, 327147-161, 331/57, 329304-310, 332127-128, 713500-503
• US Class Current: 375/376
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics
• CPC Class Codes: H04B 2215/067 by modulation dispersion

Abstract

A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

Claims

1. A method for generating clock signals, comprising:

generating a second clock signal based on a first frequency modulated clock signal output from a spread-spectrum clock generator;

detecting a phase difference between the second clock signal and the first modulated clock signal; and

delaying the second clock signal based on a period of the first frequency modulated clock signal to reduce said phase difference, wherein said delaying includes;

(a) measuring the period of the first modulated clock signal;

(b) measuring a delay between the second clock signal and the first modulated clock signal; and

(c) generating a first control signal to adjust the delay of the second clock signal, to thereby reduce mis-alignment between the second clock signal and the first modulated clock signal, based on results of (a) and (b), wherein the delaying further includes;

(d) generating a second control signal from a phase detector to adjust the delay of the second clock signal to thereby reduce mis-alignment between the second clock signal and the first modulated clock signal, said phase detector also detecting said phase difference.

2. The method of claim 1, wherein said generating includes delaying the second clock signal relative to the first modulated clock signal.

3. The method of claim 1, wherein the second control signal delays the second clock signal relative to the first clock signal by a first amount of time.

4. The method of claim 3, wherein the first control signal delays the second clock signal relative to the first modulated clock signal by a second amount of time greater than the first amount of time.

5. The method of claim 4, wherein the second clock signal is delayed by the first amount of time by a fine tuning delay line and is delayed by the second amount of time by a coarse tuning delay line.

6. The method of claim 5, wherein (a) is performed by a first time-to-digital converter which converts the period of the first clock signal into a first digital signal, and (b) is performed by a second time-to-digital converter which converts the delay of the second clock signal into a second digital signal, and wherein a controller generates the first control signal for adjusting the coarse tuning line based on a comparison of the first and second digital signals.

7. The method of claim 1, wherein the first modulated clock signal is generated from a processor located on a motherboard of a computer.

8. The method of claim 7, further comprising:

operating a peripheral device based on the modified second clock signal.

9. A system for generating clock signals, comprising:

a delay-locked loop which generates a second clock signal based on a first frequency modulated clock signal output from a spread-spectrum clock generator, said loop including

a phase detector which determines a phase difference between the second clock signal and the first modulated clock signal and

a voltage-controlled delay chain circuit which generates a first control signal for delaying the second clock signal to reduce said phase difference, wherein the voltage-controlled delay chain circuit generates the first control signal based on a period of the first frequency modulated clock signal, and includes;

(a) a first circuit which measures the period of the first modulated clock signal; and

(b) a second circuit which measures a delay between the second clock signal and the first modulated clock signal, and

(c) a controller which generates the first control signal to delay the second clock signal to reduce said phase difference based on said delay and said measured period,

wherein the phase detector generates a second control signal to reduce said phase difference, and wherein the first control signal delays the second clock signal by a first amount and the second control signal delays the second clock signal by a second amount, where the first amount is greater than the second amount.

10. A method for generating clock signals, comprising:

generating a second clock signal based on a first frequency modulated clock signal output from a spread spectrum clock generator;

detecting a phase difference between the second clock signal and the first clock signal; and

modifying the second clock signal to reduce said phase difference, wherein said modifying includes;

coarsely tuning the second clock signal by a first total delay amount based on a period of the first frequency modulated clock signal, and finely tuning the second clock signal by a second total delay amount,

wherein the first clock signal and the second clock signal are digital signals, the first total delay amount is at least one of a plurality of first amounts, the second total delay amount is at least one of a plurality second amounts, with the second amounts being less than the first amounts, and

wherein said coarse tuning includes;

(a) measuring the period of the first clock signal,

(b) measuring a delay between the second clock signal and the first clock signal, and

(c) reducing mis-alignment between the second clock signal and the first clock signal by the first total delay amount based on results of (a) and (b).

11. The method of claim 10, wherein said fine tuning includes generating a control signal from a phase detector to delay the second clock signal by the second total delay amount, thereby reducing mis-alignment between the second clock signal and the first clock signal.

12. The method of claim 10, wherein the second clock signal is modified to reduce said phase difference to substantially zero.

13. A method for generating clock signals, comprising:

generating a second clock signal based on a first frequency modulated clock signal output from a spread-spectrum clock generator;

detecting a phase difference between the second clock signal and the first modulated clock signal; and

delaying the second clock signal based on a period of the first frequency modulated clock signal to reduce said phase difference, wherein said delaying comprises;

determining the period of the first frequency modulated clock signal;

determining a delay time of the second clock signal; and

delaying the second clock signal based on a comparison of the period of the first frequency modulated clock signal and the delay time of the second clock signal, and

wherein the period of the first frequency modulated clock signal is determined by calculating a number of delay taps in the first frequency modulated clock signal, and the delay time of the second clock signal is determined by calculating a number of delay taps in the second clock signal, and wherein the second clock signal is delayed based on a comparison of the numbers of delay taps calculated for the first frequency modulated clock signal and the second clock signal.

14. A system for generating clock signals, comprising:

a delay-locked loop which generates a second clock signal based on a first frequency modulated clock signal output from a spread-spectrum clock generator, said loop including

a phase detector which determines a phase difference between the second clock signal and the first modulated clock signal and

a voltage-controlled delay chain circuit which generates a first control signal for delaying the second clock signal to reduce said phase difference, wherein the voltage-controlled delay chain circuit generates the first control signal based on a period of the first frequency modulated clock signal and wherein the voltage-controlled delay chain circuit generates the first control signal by;

(a) determining the period of the first frequency modulated clock signal;

(b) determining a delay time of the second clock signal; and

(c) comparing the period of the first frequency modulated clock signal and the delay time of the second clock signal, and

wherein the voltage-controlled delay chain circuit determines the period of the first frequency modulated clock signal by calculating a number of delay taps in the first frequency modulated clock signal, determines the delay time of the second clock signal by calculating a number of delay taps in the second clock signal, and generates the first control signal based on a comparison of the numbers of delay taps calculated for the first frequency modulated clock signal and the second clock signal.

15. A system for generating clock signals, comprising:

a delay-locked loop which generates a second clock signal based on a first frequency modulated clock signal output from a spread-spectrum clock generator, said loop including

a phase detector which determines a phase difference between the second clock signal and the first modulated clock signal; and

a voltage-controlled delay chain circuit which generates a first control signal for delaying the second clock signal to reduce said phase difference, wherein the voltage-controlled delay chain circuit generates the first control signal based on a period of the first frequency modulated clock signal, and wherein the voltage-controlled delay chain circuit includes;

a first time-to-digital converter which converts the period of the first frequency modulated clock signal into a first digital signal,

a second time-to-digital converter which converts the delay of the second clock signal into a second digital signal, and

a controller which generates the first control signal for delaying the second clock signal based on a comparison of the first and second digital signals.

16. The system of claim 15, wherein the phase detector generates a second control signal for delaying the second clock signal.

17. The system of claim 16, wherein the first control signal adjusts a coarse delay and the second control signal adjusts a fine delay of the second clock signal.

18. A method for generating clock signals, comprising:

generating a second clock signal based on a first frequency modulated clock signal output from a spread spectrum clock generator;

detecting a phase difference between the second clock signal and the first clock signal; and

modifying the second clock signal to reduce said phase difference, wherein said modifying includes;

coarsely tuning the second clock signal by a first total delay amount based on a period of the first frequency modulated clock signal, and finely tuning the second clock signal by a second total delay amount, and

wherein coarsely tuning the second clock signal includes;

determining the period of the first frequency modulated clock signal;

determining a delay time of the second clock signal; and

comparing the period of the first frequency modulated clock signal and the delay time of the second clock signal, said coarse tuning being performed based on a result of the comparison.

19. The method of claim 18, wherein the period of the first frequency modulated clock signal is determined by calculating a number of delay taps in the first frequency modulated clock signal, the delay time of the second clock signal is determined by calculating a number of delay taps in the second clock signal, and said comparing includes comparing the numbers of delay taps calculated for the first frequency modulated clock signal and the second clock signal.

20. A method for generating clock signals, comprising:

generating a second clock signal based on a first frequency modulated clock signal output from a spread spectrum clock generator;

detecting a phase difference between the second clock signal and the first clock signal; and

modifying the second clock signal to reduce said phase difference, wherein said modifying includes;

coarsely tuning the second clock signal by a first total delay amount based on a period of the first frequency modulated clock signal, and finely tuning the second clock signal by a second total delay amount, and

wherein coarsely tuning the second clock signal includes;

converting the period of the first clock signal into a first digital signal using a first time-to-digital converter;

converting a delay of the second clock signal into a second digital signal using a second time-to-digital converter; and

coarsely tuning the second clock signal based on a comparison of the first and second digital signals.