Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications

• US 6,993,307 B2
• Filed: 10/08/2003
• Issued: 01/31/2006
• Est. Priority Date: 05/29/1998
• Status: Expired due to Term

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Wang, Caiyi, Welland, David R.
• Primary Examiner(s): Gesesse, Tilahun
• Application Number:
  US10/681,405
• Publication Number:
  US 20040075506A1
• Time in Patent Office: 846 Days
• Field of Search: 455/76, 455/85, 455/88, 455/260, 455/163.1, 331/36.V, 331/16, 331/36.C, 331/36.R, 327/159
• US Class Current: 455/260
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/187 using means for coarse tuning the voltage controlled oscillator of the loop H03L7/191 - H03L7/195 take precedence
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may include an analog control loop in which a phase detector circuit and sample and hold circuit are utilized. The output of the sample and hold circuit may be provided to the PLL VCO as VCO input control signals.

Claims

1. A frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator having an output frequency dependent upon a plurality of different analog control signals, the plurality of different analog control signals being received by the controllable oscillator as different frequency control input signals such that at least some of the plurality of control signals are configured to individually control the output frequency of the controllable oscillator without being combined with others of the plurality of control signals;

a phase detector configured to concurrently provide a plurality of different analog output signals, the plurality of different analog output signals being generated from a phase difference between at least two input signals; and

a sample and hold circuit coupled to sample each of the plurality of different analog output signals from the phase detector and to hold a plurality of different sampled analog output signals, the plurality of different sampled analog output signals from the sample and hold circuit being used to provide the plurality of different analog control signals for the controllable oscillator.

2. The frequency synthesizer of claim 1, wherein the input signals to the phase detector comprise a first input signal coupled to an output of the controllable oscillator and a second input signal coupled to a reference signal.

3. The frequency synthesizer of claim 1, wherein the input signals to the phase detector comprise a plurality of first input signals based upon an output of the controllable oscillator and at least one other second input signal coupled to a reference signal, the plurality of analog output signals being generated from the phase differences between the plurality of first input signals and the at least one other second input signal.

4. The frequency synthesizer of claim 3, wherein the number of first input signals and the number of analog output signals is equal.

5. The frequency synthesizer of claim 3, wherein the number of analog output signals is at least five.

6. The frequency synthesizer of claim 3, wherein the number of analog output signals is at least twenty.

7. The frequency synthesizer of claim 3, wherein the plurality of first input signals are signals having at least one phase shifted edge with respect to each other.

8. The frequency synthesizer of claim 7, further comprising a shift register having the plurality of phase shifted signals as outputs.

9. The frequency synthesizer of claim 3, wherein the phase detector comprises a plurality of phase detector sub-circuits, each sub-circuit having as an output one of the plurality of analog output signals and having as inputs at least one of the plurality of first signals and at least one of the second signals.

10. Phase locked loop circuitry for generating an output signal at a variable output frequency, comprising:

a controllable oscillator having an output signal at an output frequency dependent upon a plurality of different analog control signals, the plurality of different analog control signals being received by the controllable oscillator as different frequency control input signals such that at least some of the plurality of analog control signals are configured to individually control the output freciuency of the controllable oscillator without being combined with others of the plurality of analog control signals; and

phase difference control circuitry configured to concurrently provide the plurality of different analog control signals as outputs, the plurality of different analog control signals being generated from a phase difference between at least two input signals;

wherein the controllable oscillator comprises a plurality of non-varactor diode capacitance circuits connected in parallel to contribute a combined capacitance amount that determines at least in part the output frequency of the controllable oscillator, the plurality of different analog control signals from the phase difference control circuitry being coupled to control the amount of capacitance contributed by the plurality of capacitance circuits.

11. The phase locked loop circuitry of claim 10, wherein the phase difference control circuitry comprises a phase detector configured to receive the at least two input signals and to output a plurality of different analog output signals based upon phase differences and sample-and-hold circuitry configured to receive the plurality of different analog output signals and to output the plurality of different analog control signals.

12. The phase locked loop circuitry of claim 10, wherein the controllable oscillator comprises an LC tank resonant structure including the plurality of capacitance circuits.

13. The phase locked loop circuitry of claim 10, wherein the each of the plurality of capacitance circuits comprises at least one capacitor and a variable resistance element, the variable resistance element being coupled to at least one of the plurality of analog control signals.

14. The phase locked loop circuitry of claim 13, wherein the variable resistance element comprises a transistor and wherein at least one capacitor is coupled to the source or drain of the transistor and the control signal is coupled to the gate of the transistor.

15. The phase locked loop circuitry of claim 14, further comprising at least a second capacitor coupled between the source and drain of the transistor.

16. The phase locked loop circuitry of claim 10, wherein at least one of the input signals to the phase difference control circuitry is adjustable and is configured to determine at least in part the frequency of the output signal.

17. The phase locked loop circuitry of claim 16, wherein one input signal to the phase difference control circuitry is an adjustably divided version of the output signal and a second input signal to the phase difference control circuitry is an adjustably divided version of a reference signal, the first and second.

18. A method of operating phase locked loop circuitry for generating an output signal at a variable output frequency, comprising:

controlling an output frequency of a controllable oscillator utilizing at least in part a plurality of different analog control signals, the plurality of different analog control signals being received by the controllable oscillator as different frequency control input signals such that at least some of the plurality of analog control signals are configured to individually control the output frequency of the controllable oscillator without being combined with others of the plurality of analog control signals; and

detecting a phase difference between at least two input signals with phase difference control circuitry to concurrently provide the plurality of different analog control signals as outputs;

wherein the controllable oscillator comprises a plurality of non-varactor diode capacitance circuits connected in parallel to contribute a combined capacitance amount that determines at least in part the output frequency of the controllable oscillator, the plurality of different analog control signals from the phase difference control circuitry being coupled to control the amount of capacitance contributed by the plurality of capacitance circuits.

20. The method of claim 18, wherein the controllable oscillator comprises an LC tank resonant structure including the plurality of capacitance circuits.

21. The method of claim 18, wherein the each of the plurality of capacitance circuits comprises at least one capacitor and a variable resistance element, the variable resistance element being coupled to at least one of the plurality of analog control signals.

22. The method of claim 21, wherein the variable resistance element comprises a transistor, wherein at least one capacitor is coupled to the source or drain of the transistor, and wherein the control signal is coupled to the gate of the transistor.

23. The method of claim 18, further comprising adjusting at least one of the input signals to the phase difference control circuitry to determine at least in part the frequency of the output signal.

24. The method of claim 23, wherein one input signal to the phase difference control circuitry is an adjustable divided version of the output signal and a second input signal to the phase difference control circuitry is an adjustable divided version of a reference signal, the first and second.

19. The method of 18, wherein the detecting step comprises detecting a phase difference between at least two input signals, generating a plurality of different analog output signals based upon phase differences, sampling the plurality of different analog output signals, and holding a plurality of sampled analog output signals to provide the plurality of different analog control signals.