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Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications

  • US 6,993,307 B2
  • Filed: 10/08/2003
  • Issued: 01/31/2006
  • Est. Priority Date: 05/29/1998
  • Status: Expired due to Term
First Claim
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1. A frequency synthesizer having a phase locked loop, comprising:

  • a controllable oscillator having an output frequency dependent upon a plurality of different analog control signals, the plurality of different analog control signals being received by the controllable oscillator as different frequency control input signals such that at least some of the plurality of control signals are configured to individually control the output frequency of the controllable oscillator without being combined with others of the plurality of control signals;

    a phase detector configured to concurrently provide a plurality of different analog output signals, the plurality of different analog output signals being generated from a phase difference between at least two input signals; and

    a sample and hold circuit coupled to sample each of the plurality of different analog output signals from the phase detector and to hold a plurality of different sampled analog output signals, the plurality of different sampled analog output signals from the sample and hold circuit being used to provide the plurality of different analog control signals for the controllable oscillator.

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