Apparatus for generating multiple radio frequencies in communication circuitry and associated methods

• US 6,993,314 B2
• Filed: 02/13/2002
• Issued: 01/31/2006
• Est. Priority Date: 05/29/1998
• Status: Expired due to Term

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Scott, Jeffrey W., Lim, Lysander, Tuttle, G. Tyson, Behrens, Richard T., Vishakhadatta, G. Diwakar, Wang, Caiyi, Welland, David R., Kerth, Donald A., Srinivasan, Vishnu S.
• Primary Examiner(s): Trinh, Sonny
• Assistant Examiner(s): Cho, Un C
• Application Number:
  US10/074,591
• Publication Number:
  US 20020193084A1
• Time in Patent Office: 1,448 Days
• Field of Search: 455/260, 455/183.1, 455/183.2, 455/552.1, 455/553.1, 455/86, 455/88, 455/333, 327156-159
• US Class Current: 455/333
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/187 using means for coarse tuning the voltage controlled oscillator of the loop H03L7/191 - H03L7/195 take precedence
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics

Abstract

A radio-frequency (RF) apparatus capable of transmitting RF signals includes transmitter path circuitry. The transmitter path circuitry includes a voltage-controlled oscillator (VCO) circuitry. The VCO circuitry generates a first signal that has a first frequency. A divider circuitry couples to the VCO circuitry and, in response to the first signal, the divider circuitry generates a second signal that has a second frequency. The frequency of the second signal equals the frequency of the first signal divided by a number.

Claims

1. A radio-frequency (RF) apparatus capable of transmitting radio-frequency signals, the radio-frequency apparatus comprising:

transmitter path circuitry, including;

a voltage-controlled oscillator circuitry configured to generate a first signal that has a first frequency;

a divider circuitry being responsive to the first signal, the divider circuitry configured to generate a second signal that has a second frequency,

wherein the second frequency equals the first frequency divided by a number;

a first switch coupled to the voltage-controlled oscillator circuitry, the first switch configured to generate a switched first signal by selectively supplying the first signal to a first output;

a second switch coupled to the divider circuitry, the second switch configured to generate a switched second signal by selectively supplying the second signal to a second output; and

a feedback circuitry coupled to the voltage-controlled oscillator circuitry, the feedback circuitry configured to adjust the first frequency in response to a feedback signal derived from the switched first and second signals, and wherein the feedback circuitry comprises a third switch coupled to the first and second switches, the third switch configured to selectively supply as the feedback signal one of the switched first and second signals.

2. The radio-frequency (RF) apparatus according to claim 1, wherein the transmitter path circuitry is configured to use the switched first and second signals for multi-band radio-frequency transmission.

3. The radio-frequency (RF) apparatus according to claim 2, further configured to transmit within the DCS 1800 standard.

4. The radio-frequency (RF) apparatus according to claim 2, further configured to transmit within the GSM 900 standard.

5. An integrated circuit, comprising:

a controlled oscillator configured to generate an oscillator output signal with an adjustable frequency;

a feedback circuit coupled to the controlled oscillator, the feedback circuit configured to receive the oscillator output signal, the feedback circuit further configured to adjust the frequency of the oscillator output signal;

a frequency converter coupled to the controlled oscillator, the frequency converter configured to generate a converter output signal at a frequency that is derived from the frequency of the oscillator output signal;

a first switch coupled to the controlled oscillator, the first switch configured to selectively provide the oscillator output signal as a first output signal;

a second switch coupled to the frequency converter, the second switch configured to selectively provide the converter output signal as a second output signal, wherein the frequency of the converter output signal equals a fraction of the frequency of the oscillator output signal; and

a feedback circuit comprising a third switch coupled to the first and second switches, the third switch configured to selectively supply as a feedback signal one of the first and second output signals.

6. The integrated circuit according to claim 5, wherein the feedback circuit further comprises a first feedback circuit and a second feedback circuit.

7. The integrated circuit according to claim 6, wherein the first feedback circuit is configured to coarsely adjust the frequency of the oscillator output signal.

8. The integrated circuit according to claim 7, wherein the second feedback circuit is configured to fine tune the frequency of the oscillator output signal.

9. The integrated circuit according to claim 8, wherein the second feedback circuit is further configured to fine tune the frequency of the oscillator output signal in response to the feedback signal.

10. The integrated circuit according to claim 9, wherein the first feedback circuit is further configured to coarsely adjust the frequency of the oscillator output signal in response to a reference signal.

11. The integrated circuit according to claim 10, wherein the second feedback circuit is further configured to fine tune the frequency of the oscillator output signal in response to a radio-frequency local oscillator signal and an intermediate-frequency signal.

12. The integrated circuit according to claim 11, further comprising receiver circuitry configured to receive a radio-frequency input signal.

13. The integrated circuit according to claim 12, wherein the receiver circuitry couples to signal processing circuitry within a second integrated circuit.

14. The integrated circuit according to claim 13, wherein the receiver circuitry comprises low intermediate-frequency receiver circuitry.