System LSI

• US 6,993,447 B2
• Filed: 08/26/2003
• Issued: 01/31/2006
• Est. Priority Date: 08/26/2003
• Status: Expired due to Fees

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Yamasaki, Yoshihiro
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Barbee, Manuel L.
• Application Number:
  US10/647,221
• Publication Number:
  US 20050046434A1
• Time in Patent Office: 889 Days
• Field of Search: 702/57, 702/58, 702 81- 84, 702/108, 702117-121, 702123-125, 702182-183, 257/203, 257/207, 257/208, 324/500, 324/527
• US Class Current: 702/118
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver

Abstract

A system LSI includes a plurality of circuit blocks; a first power supply terminal, which is connected to a first circuit block; and a second power supply terminal, which is connected to a second circuit block. A first level of test voltage is applied from the first power supply terminal to the first circuit block for a predetermined period of time whereby the first circuit block is tested in operation. A second level of test voltage is applied from the second power supply terminal to the second circuit block for a predetermined period of time whereby the second circuit block is tested in operation independently from the first circuit block.

Claims

1. A system large scale integration (LSI), comprising:

first, second and third circuit blocks, each circuit block being located on a wafer;

a first power supply terminal located on the wafer and supplied with a first power supply voltage for test, wherein the first power supply voltage has a first voltage level and has a second voltage level which is different from the first voltage level;

a first power supply line located on the wafer, which surrounds the first, second and third circuit blocks, and which is connected to the first power supply terminal and the first and second circuit blocks;

a second power supply terminal located on the wafer and supplied with a second power supply voltage for test, wherein the second power supply voltage has the first voltage level and has a third voltage level which is different from the first and second voltage levels; and

a second power supply line located on the wafer, which surrounds the first, second and third circuit blocks, and which is connected to the second power supply terminal and the third circuit block.

2. A system LSI according to claim 1, wherein the first and second circuit blocks are tested on the wafer before fabrication of the system LSI is completed.

3. A system LSI according to claim 1, further comprising:

a switching circuit, connected to the second circuit block and the first and second power supply lines, that couples either one of the first and second power supply lines to the second circuit block.

4. A system LSI according to claim 3, wherein the first power supply line is surrounded by the second power supply line.

5. A system LSI according to claim 1, wherein the first power supply line is surrounded by the second power supply line.

6. A system LSI according to claim 5, wherein the first, second and third circuit blocks are tested on the wafer before fabrication of the system LSI is completed.