Terminal apparatus

• US 6,993,597 B2
• Filed: 08/13/2003
• Issued: 01/31/2006
• Est. Priority Date: 10/09/1995
• Status: Expired due to Fees

• Current Assignee: SOTA Semiconductor LLC (Acacia Research Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Nakagawa, Tetsuya, Noguchi, Koki, Baji, Toru, Hatano, Yuji, Sagesaka, Yasuhiro
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): KIM, HAROLD J
• Application Number:
  US10/639,445
• Publication Number:
  US 20040049606A1
• Time in Patent Office: 902 Days
• Field of Search: 710/5, 710/2, 710/69, 712/32, 712/35, 711/147
• US Class Current: 710/5
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 15/7807 System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Claims

1. A mobile communication terminal comprising:

a microprocessor having registers and an internal memory;

an external memory coupled with the microprocessor;

an antenna receiving a reception data from outside of the mobile communication terminal and transmitting data to outside of the mobile communication terminal; and

an RF circuit converting a frequency of the reception data and the transmission data,

wherein the microprocessor performs a CPU function and a DSP function,

wherein the microprocessor transfers a data from the internal memory to the registers per one cycle when the microprocessor performs the CPU function,

wherein the microprocessor can transfer two data from the memory to the registers per one cycle when the microprocessor performs the DSP function,

wherein the internal memory has a first internal memory and a second internal memory,

wherein the microprocessor can transfer two data from the first and second internal memories in parallel when the microprocessor performs the DSP function, and

wherein the external memory is shared by the CPU function and DSP function.

2. A mobile communication terminal according to claim 1, wherein the external memory is memory outputting data based on a clock.

3. A mobile communication terminal according to claim 1,

wherein the microprocessor outputs a first data signal corresponding to the transmission data, a first frame sync signal and a first basic clock in parallel in order to transmit the transmission data from the antenna, and

wherein the microprocessor receives a second data signal corresponding to the reception data, a second frame sync signal and a second basic clock in parallel in order to perform the reception data.

4. A mobile communication terminal according to claim 3,

wherein the first and second data signals are transferred via different signal lines,

wherein the first and second sync signals are transferred via different signal lines, and

wherein the first and second basic clock are transferred via different signal lines.

5. A mobile communication terminal according to claim 1

wherein the microprocessor performs a shift operation by using the CPU function and

wherein the microprocessor performs a FIR filter operation by using the DSP function.

6. A mobile communication terminal according to claim 1

wherein the reception data received by the antenna is performed in the microprocessor, and

wherein when the microprocessor performs the reception data by using the DSP function, a part or all the data performed by using the DSP function is stored in the external memory.

7. A mobile communication terminal according to claim 1, wherein the external memory stores the program for using both the DSP function and the CPU function.

8. A mobile communication terminal according to claim 1,

wherein the microprocessor further has an arithmetic logic unit, and

wherein the arithmetic logic unit performs an address operation for both of the CPU function and the DSP function.

9. A mobile communication terminal comprising:

a microprocessor having registers and an internal memory;

an external memory coupled to the microprocessor;

an antenna receiving a reception data from outside of the mobile communication terminal and transmitting a transmission data to outside of the mobile communication terminal, and

an RF circuit converting a frequency of the reception data and the transmission data,

wherein the microprocessor performs a program by using a CPU function or a DSP function,

wherein the internal memory has a first internal memory and a second internal memory,

wherein the microprocessor can transfer two data from the first and second internal memories in parallel when the microprocessor performs the DSP function, and

wherein the microprocessor performs the reception data by using the DSP function, the external memory stores a part or all of the data performed by using the DSP function.

10. A mobile communication terminal according to claim 9, wherein the external memory is memory outputting data based on a clock.

11. A mobile communication terminal according to claim 10,

wherein the microprocessor outputs a first data signal corresponding to the transmission data, a first frame sync signal and a first basic clock in parallel in order to transmit the transmission data from the antenna, and

wherein the microprocessor receives a second data signal corresponding to the reception data, a second frame sync signal and a second basic clock in parallel in order to perform the reception data.

12. A mobile communication terminal according to claim 11,

wherein the first and second data signals are transferred via different signal lines,

wherein the first and second sync signals are transferred via different signal lines, and

wherein the first and second basic clocks are transferred via different signal lines.

13. A mobile communication terminal according to claim 9,

wherein the microprocessor performs a shift operation using the CPU function, and

wherein the microprocessor performs a FIR filter operation by using the DSP function.

14. A mobile communication terminal according to claim 9, wherein the external memory is shared by the CPU function and the DSP function.

15. A mobile communication terminal according to claim 9, wherein the external memory stores the program for using both the DSP function and the CPU function.

16. A mobile communication terminal according to claim 9, wherein the microprocessor further has an arithmetic logic unit, and

wherein address operations for both of the CPU function and the DSP function are performed by the common arithmetic logic unit.

17. A mobile communication terminal according to claim 9,

wherein the microprocessor transfers a data from the internal memory to the registers per one cycle when the microprocessor performs the CPU function, and

wherein the microprocessor can transfer two data from the memory to the registers per one cycle when the microprocessor performs the DSP function.