Processing instruction addressed by received remote instruction and generating remote instruction to respective output port for another cell

• US 6,993,639 B2
• Filed: 04/01/2003
• Issued: 01/31/2006
• Est. Priority Date: 04/01/2003
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Ang, Boon Seong, Schlansker, Michael S.
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US10/405,170
• Publication Number:
  US 20040199745A1
• Time in Patent Office: 1,036 Days
• Field of Search: 712/18, 712/25, 712/28, 712/201
• US Class Current: 712/18
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Abstract

Embodiments of the invention relate to a processing cell for use in computing systems. Generally, a processing cell generates remote instructions to be received and processed by at least one other processing cell. A processing cell may include a program counter, an instruction memory, and appropriate elements such as a branch lookup, a branch unit, etc. Alternatively, the processing cell may include a state machine that replaces the program counter and the instruction memory. Embodiments of the invention are able to support the VLIW mode, the MIMD) mode, a mixture of both modes of execution, etc.

Claims

1. A computing system, comprising:

a plurality of processing cells including

a first processing cell having a plurality of output ports, and

a second processing cell having a plurality of input ports coupled to the plurality of output ports of the first processing cell;

wherein

a remote instruction that is transmitted by the first processing cell and tat is received by the second processing cell redirects program execution of the second processing cell to an execution address sent by the first processing cell via the remote instruction;

the remote instruction propagates from within the first processing cell to at least one selected output port of the first processing cell; and

the selected output port is configured for transporting the remote instruction to a processing cell of the plurality of processing cells based on whether that processing cell is intended to receive that remote instruction via that selected output port.

2. The computing system of claim 1 wherein an output port of the output ports of the first processing cell is associated with a bit that controls configurations of that output port.

3. The computing system of claim 1 wherein program execution on the first processing cell and the second processing cell run on clocks with known timing relationships.

4. The computing system of claim 3 wherein execution of instructions of the first processing cell and the second processing cell is scheduled based on known timing relationships between those instructions.

5. The computing system of claim 3 wherein the first processing cell and the second processing cell operate in the very-long-instruction-word mode based on

known timing relationship between the clocks run by the first processing cell and the second processing cell, and

predictability of execution of instructions of the first processing cell and the second processing cell.

6. The computing system of claim 1 wherein at least one processing cell of the plurality of processing cells operates autonomously as an independent processor.

7. The computing system of claim 1 wherein a processing cell of the plurality of processing cells includes an input combiner for receiving remote instructions from at least one other processing cell and for selecting a remote instruction of the remote instructions to be propagated into the processing cell.

8. The computing system of claim 1 wherein a processing cell of the plurality of processing cells includes:

an instruction memory that store instructions to be executed, and

a functional unit that performs an operation in response to an instruction taken from the instruction memory.

9. The computing system of claim 8 wherein the processing cell of the plurality of processing cells further includes a lookup table that converts a target portion of a remote instruction received from at least one other processing cell to an address of the instruction memory.

10. The computing system of claim 1 wherein a processing cell of the plurality of processing cells includes:

a state machine that manages executions of the processing cell, and

a functional unit that performs an operation in response to control signals from the state machine.

11. The computing system of claim 1 wherein the second processing cell forwards data associated with the remote instruction to a third processing cell.

12. The computing system of claim 1 wherein:

a portion of the plurality of processing cells is arranged into at least one cluster that comprises at least one processing cell that operates co-synchronously with other processing cells of the cluster such that execution timing relationships between processing cells of the cluster are statically predictable, and

latencies in distributing and processing remote instructions issued from a processing cell within the cluster to another cell within the cluster is predictable, and thereby permits static scheduling of processing cells within the cluster.

13. The computing system of claim 1 wherein the plurality of processing cells is arranged in a plurality of clusters each of which operates in either a very-long-instruction-word mode or a multiple-instructions-multiple-data mode.

14. The computing system of claim 1 wherein:

the plurality of processing cells includes a first cluster comprising a first plurality of processing cells and a second cluster comprising a second plurality of processing cells, and

during execution of the first cluster and the second cluster, a processing cell of the first cluster is configured to be used by the second cluster.

15. A computing system comprising:

a plurality of processing cells that are arranged in a plurality of clusters wherein program executions are synchronous within a cluster and are asynchronous between clusters;

wherein

a remote instruction that is issued by a first processing cell and that is received by a second processing cell redirects execution of the second processing cell to an execution address sent by the first processing cell; and

the remote instruction propagates within the first processing cell to a selected output port of the first processing cell; and

the selected output port is configured for transporting the remote instruction to a processing cell of the plurality of processing cells based on whether that processing cell is intended to receive the remote instruction via the selected output port.

16. A first processing cell for use in a computing system having a plurality of processing cells, comprising:

an input combiner for receiving remote instructions from a processing cell of the plurality of processing cells;

a lookup table for translating a virtual target name embedded in a remote instruction to a physical local target address to be used in instruction execution of the first processing cell;

an instruction controller for controlling destinations of instructions processed by the first processing cell;

a remote instruction generator for generating instructions for use by a second processing cell;

at least one functional unit for processing the instructions processed by the first processing cell; and

output ports for sending the instructions processed by the first processing cells for use by the second processing cell;

wherein an output port is configured for transporting an instruction for use by the second processing cell based on whether the second processing cell is intended to receive that instruction via that output port.

17. The first processing cell of claim 16 wherein the input combiner selects a remote instruction of the remote instructions based on a priority associated with the remote instruction.

18. The first processing cell of claim 16 wherein:

a remote instruction sent from the first processing cell to the second processing cell and a third processing cell triggers execution at a memory address of the second processing cell and at a memory address of the third processing cell; and

the memory address of the second processing cell differs from the memory address of the third processing cell.

19. The first processing cell of claim 16 wherein:

the virtual target name is sent from a third processing cell to the first processing cell.

20. The first processing cell of claim 16 further comprising a latch for use in pipelining the instructions processed by the first processing cell.

21. The first processing cell of claim 16 wherein the instruction controller includes:

a program counter for keeping track of instructions to be issued;

an instruction memory for storing the instructions processed by the first processing cell; and

a branch unit for determining destination and effect of an instruction for use by the second processing cell.

22. The first processing cell of claim 16 wherein the instruction controller includes a state machine for controlling operations in the first processing cell.

23. The first processing cell of claim 16 wherein:

an instruction of the instructions processed by the first processing cell is sent to the second processing cell via at least one output port of the first processing cell.

24. The first processing cell of claim 16 wherein:

an instruction processed by the first processing cell is triggered by a remote instruction received from a third processing cell via at least one output port of the third processing cell.