Methods and arrangements for automatically interconnecting cores in systems-on-chip
First Claim
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1. A method of interconnecting cores in systems-on-chip, said method comprising the steps of:
- selecting at least two cores to be interconnected, each core having at least one associated pin classified in terms of predetermined functional, structural or electrical characteristics;
automatically assessing a compatibility of at least one pin of at least one core with respect to at least one pin of at least one other core, wherein said assessing comprises performing a compatibility check to determine whether the pins of a given pair of pins are compatible with respect to at least one given characteristic;
automatically interconnecting said cores via establishing at least one connection between at least one pair of compatible pins;
prior to said selecting step, classifying said cores and said pins in terms of predetermined characteristics; and
further comprising, prior to said selecting step, encoding said characteristics as binary decision diagram variables.
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Abstract
A method and algorithms for creating correct-by-construction interconnections among complex intellectual property (IP) cores with hundreds of pins. The methods contemplated herein significantly reduce the time, complexity and potential for errors associated with systems-on-chip (SoC) integration.
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Citations
12 Claims
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1. A method of interconnecting cores in systems-on-chip, said method comprising the steps of:
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selecting at least two cores to be interconnected, each core having at least one associated pin classified in terms of predetermined functional, structural or electrical characteristics; automatically assessing a compatibility of at least one pin of at least one core with respect to at least one pin of at least one other core, wherein said assessing comprises performing a compatibility check to determine whether the pins of a given pair of pins are compatible with respect to at least one given characteristic; automatically interconnecting said cores via establishing at least one connection between at least one pair of compatible pins; prior to said selecting step, classifying said cores and said pins in terms of predetermined characteristics; and further comprising, prior to said selecting step, encoding said characteristics as binary decision diagram variables. - View Dependent Claims (2, 5, 6)
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3. A method of interconnecting cores in systems-on-chip, said method comprising the steps of:
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selecting at least two cores to be interconnected, each core having at least one associated pin classified in terms of predetermined functional, structural or electrical characteristics; automatically assessing a compatibility of at least one pin of at least one core with respect to at least one pin of at least one other core, wherein said assessing comprises performing a corruptibility check to determine whether the pins of a given pair of pins are compatible with respect to at least one given characteristic; automatically interconnecting said cores via establishing at least one connection between at least one pair of compatible pins; prior to said selecting step, classifying said cores and said pins in terms of predetermined characteristics; and wherein said assessing step further comprises performing a matching check to determine whether the pins of a given pair of pins exhibit equivalent values associated with at least one given characteristic. - View Dependent Claims (4)
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7. A system for interconnecting cores in systems-on-chip, said system comprising:
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a selector which selects at least two cores to be interconnected, each core having at least one associated pin classified in terms of predetermined functional, structural or electrical characteristics; an assessing arrangement which automatically assesses a compatibility of at least one pin of at least one core with respect to at least one pin of at least one other core, wherein said assessing arrangement is adapted to perform a compatibility check to determine whether the pins of a given pair of pins are compatible with respect to at least one given characteristic; a connecting arrangement which automatically interconnects said cores via establishing at least one connection between at least one pair of compatible pins; a classifying arrangement which classifies said cores and said pins in terms of predetermined characteristics; and further comprising an encoding arrangement which encodes said characteristics as binary decision diagram variables. - View Dependent Claims (8)
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9. A system for interconnecting cores in systems-on-chip, said system comprising:
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a selector which selects at least two cores to be interconnected, each core having at least one associated pin classified in terms of predetermined functional, structural or electrical characteristics; an assessing arrangement which automatically assesses a compatibility of at least one pin of at least one core with respect to at least one pin of at least one other core, wherein said assessing arrangement is adapted to perform a compatibility check to determine whether the pins of a given pair of pins are compatible with respect to at least one given characteristic; a connecting arrangement which automatically interconnects said cores via establishing at least one connection between at least one pair of compatible pins; and a classifying arrangement which classifies said cores and said pins in terms of predetermined characteristics, wherein said assessing arrangement is further adapted to perform a matching check to determine whether the pins of a given pair of pins exhibit equivalent values associated with at least one given characteristic. - View Dependent Claims (10, 11)
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12. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for interconnecting cores in systems-on-chip, said method comprising:
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selecting at least two cores to be interconnected, each core having at least one associated pin classified in terms of predetermined functional, structural or electrical characteristics; automatically assessing a compatibility of at least one pin of at least one core with respect to at least one pin of at least one other core, wherein said assessing comprises performing a compatibility check to determine whether the pins of a given pair of pins are compatible with respect to at least one given characteristic; automatically interconnecting said cores via establishing at least one connection between at least one pair of compatible pins; prior to said selecting step, classifying said cores and said pins in terms of predetermined characteristics; and wherein said assessing step further comprises performing a matching check to determine whether the pins of a given pair of pins exhibit equivalent values associated with at least one given characteristic.
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Specification