Methods and arrangements for automatically interconnecting cores in systems-on-chip

• US 6,993,740 B1
• Filed: 04/03/2000
• Issued: 01/31/2006
• Est. Priority Date: 04/03/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bhattacharya, Subhrajit, Bergamaschi, Reinaldo A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Levin, Naum B.
• Application Number:
  US09/542,024
• Time in Patent Office: 2,129 Days
• Field of Search: 716 1- 6, 716 12- 18, 324/765
• US Class Current: 324/762.06
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method and algorithms for creating correct-by-construction interconnections among complex intellectual property (IP) cores with hundreds of pins. The methods contemplated herein significantly reduce the time, complexity and potential for errors associated with systems-on-chip (SoC) integration.

Claims

1. A method of interconnecting cores in systems-on-chip, said method comprising the steps of:

selecting at least two cores to be interconnected, each core having at least one associated pin classified in terms of predetermined functional, structural or electrical characteristics;

automatically assessing a compatibility of at least one pin of at least one core with respect to at least one pin of at least one other core, wherein said assessing comprises performing a compatibility check to determine whether the pins of a given pair of pins are compatible with respect to at least one given characteristic;

automatically interconnecting said cores via establishing at least one connection between at least one pair of compatible pins;

prior to said selecting step, classifying said cores and said pins in terms of predetermined characteristics; and

further comprising, prior to said selecting step, encoding said characteristics as binary decision diagram variables.

2. The method according to claim 1, wherein said assessing step comprises performing Boolean operations on said binary decision diagram variables to compare and match characteristics.

5. The method according to claim 1, further comprising:

subsequent to said interconnecting step, automatically verifying whether the pins in at least one interconnected pair of pins have matching pin characteristics.

6. The method according to claim 5, further comprising:

prior to said verifying step, establishing a list of pin characteristics for which the match between the pins in at least one pair of pins is required;

said verifying step comprising the step of referring to said list of pin characteristics to determine whether the pins in at least one interconnected pair of pins have matching pin properties.

3. A method of interconnecting cores in systems-on-chip, said method comprising the steps of:

selecting at least two cores to be interconnected, each core having at least one associated pin classified in terms of predetermined functional, structural or electrical characteristics;

automatically assessing a compatibility of at least one pin of at least one core with respect to at least one pin of at least one other core, wherein said assessing comprises performing a corruptibility check to determine whether the pins of a given pair of pins are compatible with respect to at least one given characteristic;

automatically interconnecting said cores via establishing at least one connection between at least one pair of compatible pins;

prior to said selecting step, classifying said cores and said pins in terms of predetermined characteristics; and

wherein said assessing step further comprises performing a matching check to determine whether the pins of a given pair of pins exhibit equivalent values associated with at least one given characteristic.

4. The method according to claim 3, further comprising:

automatically assessing, subsequent to said interconnecting step, whether all pins are connected;

if at least two pins are not connected, thereafter applying a protocol to establish at least one additional connection between at least one additional pair of compatible pins.

7. A system for interconnecting cores in systems-on-chip, said system comprising:

a selector which selects at least two cores to be interconnected, each core having at least one associated pin classified in terms of predetermined functional, structural or electrical characteristics;

an assessing arrangement which automatically assesses a compatibility of at least one pin of at least one core with respect to at least one pin of at least one other core, wherein said assessing arrangement is adapted to perform a compatibility check to determine whether the pins of a given pair of pins are compatible with respect to at least one given characteristic;

a connecting arrangement which automatically interconnects said cores via establishing at least one connection between at least one pair of compatible pins;

a classifying arrangement which classifies said cores and said pins in terms of predetermined characteristics; and

further comprising an encoding arrangement which encodes said characteristics as binary decision diagram variables.

8. The system according to claim 7, wherein said assessing arrangement is adapted to perform Boolean operations on said binary decision diagram variables to compare and match characteristics.

9. A system for interconnecting cores in systems-on-chip, said system comprising:

a selector which selects at least two cores to be interconnected, each core having at least one associated pin classified in terms of predetermined functional, structural or electrical characteristics;

an assessing arrangement which automatically assesses a compatibility of at least one pin of at least one core with respect to at least one pin of at least one other core, wherein said assessing arrangement is adapted to perform a compatibility check to determine whether the pins of a given pair of pins are compatible with respect to at least one given characteristic;

a connecting arrangement which automatically interconnects said cores via establishing at least one connection between at least one pair of compatible pins; and

a classifying arrangement which classifies said cores and said pins in terms of predetermined characteristics, wherein said assessing arrangement is further adapted to perform a matching check to determine whether the pins of a given pair of pins exhibit equivalent values associated with at least one given characteristic.

10. The system according to claim 9, further comprising a verifying arrangement which verifies, subsequent to interconnecting, whether the pins in at least one interconnected pair of pins have matching pin characteristics.

11. The system according to claim 10, wherein said verifying arrangement is adapted to refer to a predetermined list of pin characteristics to determine whether the pins in at least one interconnected pair of pins have matching pin characteristics.

12. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for interconnecting cores in systems-on-chip, said method comprising:

selecting at least two cores to be interconnected, each core having at least one associated pin classified in terms of predetermined functional, structural or electrical characteristics;

automatically assessing a compatibility of at least one pin of at least one core with respect to at least one pin of at least one other core, wherein said assessing comprises performing a compatibility check to determine whether the pins of a given pair of pins are compatible with respect to at least one given characteristic;

automatically interconnecting said cores via establishing at least one connection between at least one pair of compatible pins;

prior to said selecting step, classifying said cores and said pins in terms of predetermined characteristics; and

wherein said assessing step further comprises performing a matching check to determine whether the pins of a given pair of pins exhibit equivalent values associated with at least one given characteristic.