High speed circuitized substrate with reduced thru-hole stub, method for fabrication and information handling system utilizing same

• US 6,995,322 B2
• Filed: 09/30/2004
• Issued: 02/07/2006
• Est. Priority Date: 01/30/2003
• Status: Expired due to Term

• Current Assignee: TTM Technologies North America, LLC (TTM Technologies Incorporated)
• Original Assignee: Endicott Interconnect Technologies Incorporated
• Inventors: Chan, Benson, Lauffer, John M.
• Primary Examiner(s): Vigushin, John B.
• Application Number:
  US10/955,741
• Publication Number:
  US 20050039950A1
• Time in Patent Office: 495 Days
• Field of Search: 361/780, 361792-795, 174/255, 174/262, 174/264, 174/266, 257/664, 257/691, 257/698, 257/728, 333/12, 333/246, 333/247
• US Class Current: 174/262
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/024 : Dielectric details, e.g. changing the dielectric material around a transmission line
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/09536 : Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/096 : Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2203/061 : of previously made multilayered subassemblies laminating only or mainly similar single-sided circuit boards H05K3/4617; laminating only or mainly similar double-sided circuit boards H05K3/462
• CPC Class Codes: H05K 3/4623 : the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: H05K 3/4688 : Composite multilayer circuits, i.e. comprising insulating layers having different properties having a special base or central core H05K3/4602
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

A circuitized substrate including a plurality of conductive and dielectric layers and also a plurality of conductive thru-holes therein for passing high speed signals, e.g., from one component to another mounted on the substrate. The substrate utilizes a signal routing pattern which uses the maximum length of each of the thru-holes wherever possible to thereby substantially eliminate signal loss (noise) due to thru-hole “stub” resonance. A multilayered circuitized substrate assembly using more than one circuitized substrate, an electrical assembly using a circuitized substrate and one or more electrical components, a method of making the circuitized substrate and an information handling system incorporating one or more circuitized substrate assemblies and attached components are also provided.

Claims

1. A high speed circuitized substrate comprising:

a plurality of electrically conductive layers;

a plurality of dielectric layers alternately positioned between selected pairs of said electrically conductive layers and electrically insulating said conductive layers from each other;

a plurality of thru-holes spacedly positioned within said substrate and extending through selected ones of said dielectric layers and said electrically conductive layers for electrically interconnecting selected ones of said electrically conductive layers to another of said electrically conductive layers to allow the passage of electrical signals between said interconnected electrically conductive layers, said electrical signals passing through the maximum length of said thru-holes so as to substantially eliminate signal loss due to thru-hole stub, said thru-holes within said substrate including a combination of internal vias, blind vias and plated through holes.

2. The high speed circuitized substrate of claim 1 wherein said plurality of electrically conductive layers are comprised of copper.

3. The high speed circuitized substrate of claim 1 wherein said plurality of dielectric layers are of a material selected from the group of materials consisting of fiberglass-reinforced epoxy resin, polytetrafluoroethylene, polyimide, polyamide, cyanate resin, photoimageable material, and combinations thereof.

4. The high speed circuitized substrate of claim 1 wherein said electrical signals are capable of passing through said substrate at a rate of from about 3.0 to about 10.0 gigabits per second.

5. The high speed circuitized substrate of claim 1 wherein the number of electrically conductive layers is from about three to about thirteen, the number of dielectric layers is from about two to about twelve, and the number of thru-holes is from about twenty to about fifty thousand.

6. A method of making a high speed circuitized substrate, said method comprising:

providing a plurality of electrically conductive layers;

providing a plurality of dielectric layers and alternately positioning selected ones of said dielectric layers between selected pairs of said electrically conductive layers so as to electrically insulate said conductive layers from each other;

forming a plurality of thru-holes within said substrate in a spaced orientation such that said plurality of thru-holes extend through selected ones of said dielectric layers and said electrically conductive layers to electrically interconnect selected ones of said electrically conductive layers to another of said electrically conductive layers so as to allow the passage of electrical signals between said interconnected electrically conductive layers, said electrical signals passing through the maximum length of said thin-holes so as to substantially eliminate

signal loss due to thru-hole stub, said forming of said plurality of thru-holes being accomplished using a laser.

7. The method of claim 6 further including bonding said plurality of electrically conductive layers and said plurality of dielectric layers together.

8. The method of claim 7 wherein said bonding is accomplished using a lamination process.

9. The method of claim 6 wherein said plurality of thru-holes include a layer of plated metal.

10. An electrical assembly comprising:

a high speed circuitized substrate including a plurality of electrically conductive layers, a plurality of dielectric layers alternately positioned between selected pairs of said electrically conductive layers and electrically insulating said conductive layers from each other, a plurality of thru-holes spacedly positioned within said substrate and extending through selected ones of said dielectric layers and said electrically conductive layers for electrically interconnecting selected ones of said electrically conductive layers to another of said electrically conductive layers to allow the passage of electrical signals between said interconnected electrically conductive layers, said electrical signals passing through the maximum length of said thru-holes so as to substantially eliminate signal loss due to thru-hole stub, said thru-holes within said substrate including a combination of internal vias, blind vias and plated through holes; and

at least one electrical component positioned on and electrically coupled to said circuitized substrate.

11. The electrical assembly of claim 10 wherein said plurality of electrically conductive layers are comprised of copper.

12. The electrical assembly of claim 10 wherein said plurality of dielectric layers are of a material selected from the group of materials consisting of fiberglass-reinforced epoxy resin, polytetrafluoroethylene, polyimide, polyamide, cyanate resin, photoimageable material, and combinations thereof.

13. The electrical assembly of claim 10 wherein said electrical signals are capable of passing through said substrate at a rate of from about 3.0 to about 10.0 gigabits per second.

14. The electrical assembly of claim 10 wherein the number of electrically conductive layers is from about three to about thirteen, the number of dielectric layers is from about two to about twelve, and the number of thru-holes is from about twenty to about fifty thousand.

15. The electrical assembly of claim 10 wherein said at least one electrical component comprises a semiconductor chip.

16. The electrical assembly of claim 10 wherein said at least one electrical component comprises a chip carrier.

17. A high speed circuitized substrate assembly comprising:

a first high speed circuitized substrate including a first plurality of electrically conductive layers and a first plurality of dielectric layers alternately positioned between selected pairs of said first electrically conductive layers and electrically insulating said first electrically conductive layers from each other;

a second high speed circuitized substrate including a second plurality of electrically conductive layers and a second plurality of dielectric layers alternately positioned between selected pairs of said second electrically conductive layers and electrically insulating said second electrically conductive layers from each other, said second circuitized substrate bonded to said first circuitized substrate to form a circuitized subassembly; and

a plurality of thru-holes positioned with said high speed circuitized subassembly and electrically interconnecting selected ones of said first and second pluralities of electrically conductive layers to allow the passage of electrical signals between said interconnected electrically conductive layers, said electrical signals passing through the maximum length of said thru-holes so as to substantially eliminate signal loss due to thru-hole stub, said thru-holes within said substrate including a combination of internal vias, blind vias and plated through holes.

18. The high speed circuitized substrate assembly of claim 17 wherein said first and second pluralities of electrically conductive layers are comprised of copper.

19. The high speed circuitized substrate assembly of claim 17 wherein said first and second pluralities of dielectric layers are of a material selected from the group of materials consisting of fiberglass-reinforced epoxy resin, polytetrafluoroethylene, polyimide, polyamide, cyanate resin, photoimageable material, and combinations thereof.

20. The high speed circuitized substrate assembly of claim 17 wherein said electrical signals are capable of passing through said substrate at a rate of from about 3.0 to about 10.0 gigabits per second.

21. The high speed circuitized substrate assembly of claim 17 wherein the number of electrically conductive layers is from about three to about thirteen, the number of dielectric layers is from about two to about twelve, and the number of thru-holes is from about twenty to about fifty thousand.

22. The invention of claim 17 wherein said circuitized substrate assembly comprises a printed circuit board.

23. The invention of claim 17 wherein said circuitized substrate assembly comprises a chip carrier.

24. The invention of claim 23 further including at least one semiconductor chip positioned on or within said chip carrier and forming part thereof.

25. An information handling system comprising:

a housing;

a high speed circuitized substrate positioned within said housing and including a plurality of electrically conductive layers, a plurality of dielectric layers alternately positioned between selected pairs of said electrically conductive layers and electrically insulating said conductive layers from each other, a plurality of thru-holes spacedly positioned within said substrate and extending through selected ones of said dielectric layers and said electrically conductive layers for electrically interconnecting selected ones of said electrically conductive layers to another of said electrically conductive layers to allow the passage of electrical signals between said interconnected electrically conductive layers, said electrical signals passing through the maximum length of said thru-holes so as to substantially eliminate signal loss due to thru-hole stub, said thru-holes within

said substrate including a combination of internal vias, blind vias and plated through holes; and

at least one electrical component positioned on and electrically coupled to said circuitized substrate.

26. The invention of claim 25 wherein said information handling system comprises a personal computer.

27. The invention of claim 25 wherein said information handling system comprises a mainframe computer.

28. The invention of claim 25 wherein said information handling system comprises a computer server.

29. A method of making a high speed circuitized substrate, said method comprising:

providing a plurality of electrically conductive layers;

providing a plurality of dielectric layers and alternately positioning selected ones of said dielectric layers between selected pairs of said electrically conductive layers so as to electrically insulate said conductive layers from each other;

forming a plurality of thru-holes including a combination of internal vias, blind vias and plated through holes within said substrate in a spaced orientation such that said plurality of thru-holes extend through selected ones of said dielectric layers and said electrically conductive layers to electrically interconnect selected ones of said electrically conductive layers to another of said electrically conductive layers so as to allow the passage of electrical signals between said interconnected electrically conductive layers, said electrical signals passing through the maximum length of said thru-holes so as to substantially eliminate signal loss due to thru-hole stub.