Apparatus and methods for semiconductor IC failure detection

• US 6,995,393 B2
• Filed: 10/02/2002
• Issued: 02/07/2006
• Est. Priority Date: 08/25/2000
• Status: Expired due to Term

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Verma, Gaurav, Weiner, Kurt H.
• Primary Examiner(s): Pham, Hoai
• Assistant Examiner(s): Farahani, Dana
• Application Number:
  US10/265,051
• Publication Number:
  US 20030071262A1
• Time in Patent Office: 1,224 Days
• Field of Search: 257/48, 257/751, 257/758, 257/765, 257/40, 257/288, 438/14, 438/17, 438/18, 324/765
• US Class Current: 257/48
• CPC Class Codes: G01N 21/66 electrically excited, e.g. electroluminescence
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01R 31/2644 Adaptations of individual semiconductor devices to facilitate the testing thereof
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01J 2237/2817 Pattern inspection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure. To produce different voltage potentials, a first set of substructures are coupled to a relatively large conductive structure, such as a large conductive pad, so that the first set of substructures charges more slowly than a second set of substructures that are not coupled to the relatively large conductive structure. Mechanisms for fabricating such a test structure are also disclosed. Additionally, searching mechanisms for quickly locating defects within such a test structure, as well as other types of voltage contrast structures, during a voltage contrast inspection are also provided.

Claims

1. A test structure that is designed for voltage contrast inspection, comprising:

a first substructure having a plurality of floating conductive structures that are designed to charge to a first potential during a voltage contrast inspection; and

a second substructure that is coupled with a conductive structure having a size selected to cause the second substructure to charge to a second potential that differs from the first potential during the voltage contrast inspection,

wherein the first and second substructures are positioned entirely within a single horizontal conductive layer without being electrically coupled with any other horizontal conductive layer.

2. A test structure as recited in claim 1, wherein the first and second substructure are not coupled to a substrate.

3. A test structure as recited in claim 1, wherein the first and second substructure are both on a same level.

4. A rest structure as recited in claim 1, wherein the second substructure includes a plurality of parallel strip segments that are each adjacent to a one of the conductive lines of the first substructure.

5. A test structure as recited in claim 4, wherein the second substructure forms a serpentine shape.

6. A test structure as recited in claim 1, wherein the second substructure is designed to charge more slowly than the first substructure during a voltage contrast inspection.

7. A test structure as recited in claim 1, wherein the second substructure is designed to have a different intensity level than the first substructure during a voltage contrast inspection.

8. A test structure as recited in claim 1, wherein the conductive structure of the second substructure has a size selected so that a partial open may be detected within the second substructure during the voltage contrast inspection.

9. A test structure as recited in claim 1, wherein the conductive structure of the second substructure has a size selected so that a complete open may be detected within the second substructure during the voltage contrast inspection.

10. A test structure as recited in claim 1, wherein the conductive structure of the second substructure has a size selected so that a short may be detected between the first and second substructure during the voltage contrast inspection.