Strained-semiconductor-on-insulator device structures

• US 6,995,430 B2
• Filed: 06/06/2003
• Issued: 02/07/2006
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: AmberWave Systems Corporation
• Inventors: Hammond, Richard, Fitzgerald, Eugene A., Lochtefeld, Anthony J., Currie, Matthew T., Langdo, Thomas A.
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): Dickey, Thomas L.
• Application Number:
  US10/456,103
• Publication Number:
  US 20040005740A1
• Time in Patent Office: 977 Days
• Field of Search: 257/18, 257/347, 257/349, 257/352, 257/E21.415, 257/E21.442, 257/E21.448, 257/E21.564, 257/E21.568, 257/E21.57, 257/E21.703, 257/E27.112, 257/E29.193, 257/E29.295, 257/E29.297, 257/E29.298, 257/E29.299
• US Class Current: 257/352
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 21/76259 with separation/delamination along a porous layer
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/66242 Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/66916 with a PN heterojunction gate
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78687 : with a multilayer structure or superlattice structure

Abstract

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Claims

1. A structure comprising:

a substrate having a dielectric layer disposed thereon; and

a strained semiconductor layer disposed in contact with the dielectric layer,

wherein the strained semiconductor layer comprises approximately 100% silicon and has a misfit dislocation density of less than about 10⁵ cm/cm².

8. The structure of claim 1, further comprising:

a transistor including;

a gate disposed above the strained semiconductor layer, the gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound.

2. A structure comprising:

a substrate having a dielectric layer disposed thereon; and

a strained semiconductor layer disposed in contact with the dielectric layer,

wherein the strained semiconductor layer comprises approximately 100% silicon and has a threading dislocation density selected from the range of about 10 dislocations/cm² to about 10⁷ dislocations/cm².

9. The structure of claim 2, further comprising:

a transistor including;

a gate disposed above the strained semiconductor layer, the gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound.

3. A structure comprising:

a substrate having a dielectric layer disposed thereon; and

a strained semiconductor layer disposed in contact with the dielectric layer,

wherein the semiconductor layer comprises approximately 100% silicon and has a surface roughness selected from the range of approximately 0.01 nm to approximately 1 nm.

10. The structure of claim 3, further comprising:

a transistor including;

a gate disposed above the strained semiconductor layer, the gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound.

4. A structure comprising:

a substrate having a dielectric layer disposed thereon; and

a strained semiconductor layer disposed in contact with the dielectric layer,

wherein the strained semiconductor layer comprises approximately 100% silicon and has a thickness uniformity across the substrate of better than approximately ±

10%.

11. The structure of claim 4, further comprising:

a transistor including;

a gate disposed above the strained semiconductor layer, the gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound.

5. A structure comprising:

a substrate having a dielectric layer disposed thereon; and

a strained semiconductor layer disposed in contact with the dielectric layer,

wherein the strained semiconductor layer comprises approximately 100% silicon and has a thickness of less than approximately 200 Å

.

12. The structure of claim 5, further comprising:

a transistor including;

a gate disposed above the strained semiconductor layer, the gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound.

6. A structure comprising:

a substrate having a dielectric layer disposed thereon; and

a strained semiconductor layer disposed in contact with the dielectric layer,

wherein the semiconductor layer comprises approximately 100% silicon and has a surface germanium concentration of less than approximately 1×

10¹² atoms/cm².

13. The structure of claim 6, further comprising:

a transistor including;

a gate disposed above the strained semiconductor layer, the gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound.

7. A structure comprising:

a substrate having a dielectric layer disposed thereon; and

a strained semiconductor layer disposed in contact with the dielectric layer,

wherein an interface between the strained semiconductor layer and the dielectric layer has a density of bonding voids of less than 0.3 voids/cm².

14. The structure of claim 7, further comprising:

a transistor including;

a gate disposed above the strained semiconductor layer, the gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound.