High-performance CMOS SOI devices on hybrid crystal-oriented substrates
First Claim
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1. An integrated circuit structure comprising:
- a substrate having at least two types of crystalline orientations;
first-type transistors formed on first portions of said substrate having a first type of crystalline orientation;
second-type transistors formed on second portions of said substrate having a second type of crystalline orientation different from the first type of crystalline orientation; and
a straining layer above said first-type transistors and said second-type transistors,wherein said first portions of said substrate comprise a first layer at a top of said first portions, said first layer having said first type of crystalline orientation and a second layer at a bottom of said first portions, said second layer having said second type of crystalline orientation, andwherein said second portions of said substrate comprise said second layer at a bottom of said second portions and a third layer at a top of said second portions, said third layer having said second type of crystalline orientation and said third layer contacting said second layer;
wherein said first-type transistors and said second-type transistors include silicide regions and said straining layer is above said silicide regions; and
,wherein said integrated circuit structure further comprises an insulator layer separating said first layer from said second layer.
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Abstract
Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. The first-type transistors are on first portions of the substrate that have a first type of crystalline orientation and second-type transistors are on second portions of the substrate that have a second type of crystalline orientation. The straining layer is above the first-type transistors and the second-type transistors. Further, the straining layer can be strained above the first-type transistors and relaxed above the second-type transistors.
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Citations
10 Claims
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1. An integrated circuit structure comprising:
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a substrate having at least two types of crystalline orientations; first-type transistors formed on first portions of said substrate having a first type of crystalline orientation; second-type transistors formed on second portions of said substrate having a second type of crystalline orientation different from the first type of crystalline orientation; and a straining layer above said first-type transistors and said second-type transistors, wherein said first portions of said substrate comprise a first layer at a top of said first portions, said first layer having said first type of crystalline orientation and a second layer at a bottom of said first portions, said second layer having said second type of crystalline orientation, and wherein said second portions of said substrate comprise said second layer at a bottom of said second portions and a third layer at a top of said second portions, said third layer having said second type of crystalline orientation and said third layer contacting said second layer; wherein said first-type transistors and said second-type transistors include silicide regions and said straining layer is above said silicide regions; and
,wherein said integrated circuit structure further comprises an insulator layer separating said first layer from said second layer. - View Dependent Claims (2, 3, 4, 5)
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6. An integrated circuit structure comprising:
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a substrate having at least two types of crystalline orientations; N-type field effect transistors (NFETs) formed on first portions of said substrate having a first type of crystalline orientation; P-type field effect transistors (PFETs) formed on second portions of said substrate having a second type of crystalline orientation different from the first type of crystalline orientation; and a straining layer above said NFETs and said PFETs, wherein one of said first portions and said second portions of said substrate comprise a first layer at a top, said first layer having said first type of crystalline orientation and a second layer at a bottom, said second layer having said second type of crystalline orientation, and wherein the other of said first portions and said second portions of said substrate comprise said second layer at a bottom and a third layer at a top, said third layer having said second type of crystalline orientation and said third layer contacting said second layer; wherein said NFETs and said PFETs include silicide regions and said straining layer is above said silicide regions; and
,wherein said integrated circuit structure further comprises an insulator layer separating said first layer from said second layer. - View Dependent Claims (7, 8, 9, 10)
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Specification