Multilevel copper interconnects with low-k dielectrics and air gaps

• US 6,995,470 B2
• Filed: 02/25/2004
• Issued: 02/07/2006
• Est. Priority Date: 05/31/2000
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US10/786,354
• Publication Number:
  US 20040164419A1
• Time in Patent Office: 713 Days
• Field of Search: 257758-760, 438/619, 438622-624, 438/421, 438/422
• US Class Current: 257/758
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which further reduces both intra-level line to line capacitance and the inter-level capacitance.

In particular, an illustrative embodiment of the present invention includes a novel methodology for forming multilevel wiring interconnects in an integrated circuit assembly. The method includes forming a number of multilayer metal lines, e.g. copper lines formed by selective electroless plating, separated by air gaps above a substrate. A low dielectric constant material is deposited between the number of metal lines and the substrate using a directional process. According to the teachings of the present invention, using a directional process includes maintaining a number of air gaps in the low dielectric constant material. Structures and systems are similarly included in the present invention.

Claims

1. A multilevel wiring interconnect in an integrated circuit, comprising:

a number of multilayer metal lines connecting to a number of silicon devices in a substrate;

a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate;

wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material; and

wherein the low dielectric constant insulator includes a film in which of a set of methyl groups and a fluorine group of atoms are as much as 43% and 9% respectively of that for a content of silicon atoms in the film.

2. The multilevel wiring interconnect of claim 1, wherein the low dielectric constant insulator includes a low dielectric constant organic silica film.

3. The multilevel wiring interconnect of claim 1, wherein the low dielectric constant insulator includes a low dielectric constant insulator having a dielectric constant (k) of less than 2.7.

4. The multilevel wiring interconnect of claim 1, wherein the number of multilayer metal lines includes a number of multilayer metal lines selected from the group consisting of Aluminum, Copper, Silver, and Gold.

5. The multilevel wiring interconnect of claim 1, wherein the number of multilayer metal lines includes a first conductor bridge level.

6. A multilevel wiring interconnect system, comprising:

a number of multilayer metal lines connecting to a number of integrated circuit devices in a substrate;

a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate, the low dielectric constant insulator having a number of air gaps therein; and

wherein the low dielectric constant insulator includes a film in which of a set of methyl groups and a fluorine group of atoms are as much as 43% and 9% respectively of that for a content of silicon atoms in the film.

7. The system of claim 6, wherein the number of multilayer metal lines are adapted to connect to at least one of a processor and a memory.

8. The system of claim 6, wherein the substrate is a die.

10. The system of claim 6, wherein the number of multilayer metal lines consist essentially of copper.

9. The system of claim, wherein the substrate includes a silicon.

11. A system having a multilevel wiring interconnect, comprising:

an integrated circuit device; and

an integrated memory circuit operably coupled to the integrated circuit device, wherein the integrated memory circuit includes a multilevel wiring interconnect, the multilevel wiring interconnect comprising;

a number of multilayer Copper lines connecting to one or more of the transistors in a substrate;

a low dielectric constant insulator in a number of interstices between the number of multilayer Copper lines and the substrate;

wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material; and

wherein the low dielectric constant insulator includes a film in which of a set of methyl groups and a fluorine group of atoms are as much as 43% and 9% respectively of that for a content of silicon atoms in the film.

12. The system of claim 11, wherein the integrated circuit device includes a processor.

13. A system, comprising:

a processor; and

an integrated memory circuit coupled to the processor, wherein the integrated memory circuit further includes a multilevel wiring interconnect, the multilevel wiring interconnect comprising;

a number of multilayer Copper lines connecting to one or more of the transistors in a substrate;

a low dielectric constant insulator in a number of interstices between the number of multilayer Copper lines and the substrate;

wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material; and

wherein the low dielectric constant insulator includes a film in which of a set of methyl groups and a fluorine group of atoms are as much as 43% and 9% respectively of that for a content of silicon atoms in the film.

14. The system of claim 13, wherein the low dielectric constant insulator includes a low dielectric constant organic silica film.

15. The system of claim 13, wherein the low dielectric constant insulator includes a low dielectric constant insulator having a dielectric constant of less than 2.7.